具有分类访问顺序的伪多组DRAM

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797260

S. Shiratake, K. Tsuchida, H. Toda, H. Kuyama, M. Wada, F. Kouno, T. Inaba, H. Akita, K. Isobe

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引用次数: 5

摘要

提出了一种新的结构，在实现大带宽的同时，核心电路几乎与传统DRAM相同。改进的行块激活方案与分类访问序列相结合，即使采用共享感测放大器方案，也提高了DRAM的带宽。提出的延迟写操作有效地填补了从写到读的命令间隙，提高了随机读写混合周期的数据效率。该架构已在采用0.15 /spl μ m CMOS工艺制造的128 Mbit测试车上成功地进行了测试。

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A pseudo multi-bank DRAM with categorized access sequence

A new architecture which realizes the large bandwidth with virtually the same core circuitry as a conventional DRAM is proposed. The improved row block activation scheme combined with a categorized access sequence improves the bandwidth of the DRAM even with the shared sense amplifier scheme. The data efficiency of the random read/write mixed cycle is improved by the proposed delayed write operation, which fills the write to read command gap effectively. The proposed architecture is successfully examined in the 128 Mbit test vehicle fabricated with a 0.15 /spl mu/m CMOS process.

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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