Future perspective and scaling down roadmap for RF CMOS

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-14 DOI:10.1109/VLSIT.1999.799394

E. Morifuji, H. Momose, T. Ohguro, T. Yoshitomi, H. Kimijima, F. Matsuoka, M. Kinugawa, Y. Katsumata, H. Iwai

引用次数: 32

Abstract

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.

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RF CMOS的未来展望和缩小路线图

基于仿真和实验，研究了RF CMOS在fT、fmax、RF噪声、线性度和匹配特性方面的未来缩小概念。研究发现，栅极宽度和指长是关键参数，特别是在小于100 nm栅极长度世代中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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