一种持续减少CPU等待周期的DRAM系统

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797261

Y. Kanno, H. Mizuno, T. Watanabe

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引用次数: 2

摘要

本文描述了一种在基于缓存的存储器层次结构中持续减少访问DRAM的CPU等待周期的DRAM系统。算术地址映射电路和伪双端口DRAM访问协议提供了没有银行冲突的DRAM访问和高速回写访问(写脏数据和读缓存线填充)。该实现只需要用于地址映射电路的两个加法器和每个DRAM中的一个数据预加载寄存器。

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A DRAM system for consistently reducing CPU wait cycles

This paper describes a DRAM system for consistently reducing CPU wait cycles for an access to DRAMs in a cache-based memory hierarchy. An arithmetical address mapping circuitry and a pseudo dual-port DRAM access protocol provide a DRAM access without a bank conflict and high speed write-back accesses (write for dirty data and read for cache-line filling). Only two adders for the address mapping circuitry and a data-preload register in each DRAM are necessary for the implementation.

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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