GAD:用于均衡多级链路的12gs /s CMOS 4位A/D转换器

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797232

W. Ellersick, Chih-Kong Ken Yang, Mark Horowitz, William J. Dally

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引用次数: 56

摘要

在0.25-/spl mu/m CMOS工艺下，制作了一个4位12gsample /sec A/D转换器(GAD)，用于研究均衡多级链路的设计。时钟差分放大器用于采样输入，然后是高速比较器与电流求和偏移抵消。输入带宽测量为2.5 GHz。8个1.5 gsample /sec的闪存A/D转换器相互交错，以实现总采样率。

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GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link

A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-/spl mu/m CMOS process to investigate the design of an equalized multi-level link. Clocked differential amplifiers were used to sample the input, followed by high-speed comparators with current-summed offset cancellation. Input bandwidth was measured at 2.5 GHz. Eight 1.5-GSample/sec flash A/D converters were interleaved to achieve the aggregate sample rate.

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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