M. Nagata, M. Homma, Noriaki Takeda, Takashi Morie, Atsushi Iwata
{"title":"具有像素级PWM信号处理的智能CMOS成像仪","authors":"M. Nagata, M. Homma, Noriaki Takeda, Takashi Morie, Atsushi Iwata","doi":"10.1109/VLSIC.1999.797265","DOIUrl":null,"url":null,"abstract":"A PWM signal CMOS imager which realizes block averaging and 2D projection of a thresholded image, in addition to row-parallel PWM readout with high-resolution gray scale, is reported. A pixel including a photo detector executes nondestructive conversion of integrated photo current to PWM signals or binary signals, which drives a readout bus in voltage or current mode. The average and 2D projection are realized with PWM signal addition techniques based on switched current integration and charge packet counting. An experimental imager including 56/spl times/56 pixels, an address signal generator, and a signal processing circuit are fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology. The PWM imager consumes only 2 /spl mu/W/pixel at a 3.3 V supply voltage for a readout operation.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A smart CMOS imager with pixel level PWM signal processing\",\"authors\":\"M. Nagata, M. Homma, Noriaki Takeda, Takashi Morie, Atsushi Iwata\",\"doi\":\"10.1109/VLSIC.1999.797265\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A PWM signal CMOS imager which realizes block averaging and 2D projection of a thresholded image, in addition to row-parallel PWM readout with high-resolution gray scale, is reported. A pixel including a photo detector executes nondestructive conversion of integrated photo current to PWM signals or binary signals, which drives a readout bus in voltage or current mode. The average and 2D projection are realized with PWM signal addition techniques based on switched current integration and charge packet counting. An experimental imager including 56/spl times/56 pixels, an address signal generator, and a signal processing circuit are fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology. The PWM imager consumes only 2 /spl mu/W/pixel at a 3.3 V supply voltage for a readout operation.\",\"PeriodicalId\":433264,\"journal\":{\"name\":\"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1999.797265\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1999.797265","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A smart CMOS imager with pixel level PWM signal processing
A PWM signal CMOS imager which realizes block averaging and 2D projection of a thresholded image, in addition to row-parallel PWM readout with high-resolution gray scale, is reported. A pixel including a photo detector executes nondestructive conversion of integrated photo current to PWM signals or binary signals, which drives a readout bus in voltage or current mode. The average and 2D projection are realized with PWM signal addition techniques based on switched current integration and charge packet counting. An experimental imager including 56/spl times/56 pixels, an address signal generator, and a signal processing circuit are fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology. The PWM imager consumes only 2 /spl mu/W/pixel at a 3.3 V supply voltage for a readout operation.