10-100 Gb/s吞吐量CMOS技术

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797238

C. Svensson, A. Edman

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引用次数: 1

摘要

描述了CMOS中高数据吞吐量芯片的基本限制，并讨论了应对这些限制的方法。通过两个设计实例证明了所提出的方法:用于高吞吐量协议处理的流水线数据路径架构;以及用于交换的共享缓冲架构。

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10-100 Gb/s throughput CMOS techniques

Basic limitations to high data throughput chips in CMOS are described and methods for coping with these discussed. The proposed methods are demonstrated by two design examples;: a pipelined datapath architecture for high throughput protocol processing; and a shared buffer architecture for switching.

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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