A 12.4 mW CMOS front-end for a 5 GHz wireless-LAN receiver

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797245

H. Samavati, H. Rategh, T. Lee

引用次数: 18

Abstract

This paper presents a 12.4 mW front-end for a 5 GHz wireless-LAN receiver fabricated in a 0.24 /spl mu/m CMOS technology. It consists of an LNA, mixers and an automatically tuned third-order filter controlled by a low-power PLL. The filter attenuates the image-signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm.

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12.4 mW CMOS前端，用于5ghz无线局域网接收器

本文提出了一种采用0.24 /spl mu/m CMOS工艺制作的用于5ghz无线局域网接收机的12.4 mW前端。它由LNA、混频器和由低功率锁相环控制的自动调谐三阶滤波器组成。该滤波器对图像信号的衰减比图像抑制结构所能达到的额外衰减12db。该滤波器还降低了LNA核心中级联码器件的噪声贡献。LNA/滤波器组合的噪声系数为4.8 dB，信号路径的总噪声系数为5.2 dB。整体IIP3为-2 dBm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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