{"title":"Stability and Performance Optimization of 6T SRAM Cell at Cryogenic Temperature","authors":"Shao-Fu Fang, V. Hu","doi":"10.1109/EDTM55494.2023.10103047","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103047","url":null,"abstract":"Cryogenic on-chip memory is viable for obtaining high-performance computing (HPC) or power reduction. Cryogenic SRAM (Cryo-SRAM) with low threshold voltage (LVT) design at reduced supply voltage (VDD) gets the maximized speed-power gain thanks to the steep subthreshold slope (SS) of cryo-CMOS. However, SRAM with LVT design at 77K may suffer the stability issue. This work demonstrates the optimized threshold voltage design for 6T cryo-SRAM. Compared to the SRAM with LVT design at 77K, the optimized 6T cryo-SRAM cells improve the read and hold static noise margin by 25% and 12%, respectively. Moreover, the optimized 6T cryo-SRAM preserves the speed-power advantages compared to 300K 6T SRAM with standard threshold voltage (SVT) design. The optimized 6T cryo-SRAMs with fast speed and superior stability could be promising candidates for HPC applications.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123630930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kyungnam Kang, Seongmin Im, Changhun Lee, Jungho Kim, Donghyun Kim
{"title":"Optimized metasurface design for enhanced organic light-emitting diodes","authors":"Kyungnam Kang, Seongmin Im, Changhun Lee, Jungho Kim, Donghyun Kim","doi":"10.1109/EDTM55494.2023.10103109","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103109","url":null,"abstract":"We optimized the structural parameters of the metasurface (MS) for enhanced bottom-emitting organic light-emitting diodes (B-OLEDs). MS consists of mixed metallic nanoslot arrays. The performance of MS-integrated B-OLED is estimated by out-coupling efficiency and reflection of the ambient light. The layer thicknesses of the capping layer and the MS which affect the excitation of surface plasmon are optimized and the width and length of nanoslot are determined by reducing reflectance caused by localized SP. The optimized metasurface enhances performances by 16% over the conventional B-OLED.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117168291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis and Modeling of OFF-State Capacitance in LDD MOSFETs","authors":"Ayushi Sharma, R. Goel, Y. Chauhan","doi":"10.1109/EDTM55494.2023.10102983","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10102983","url":null,"abstract":"Since the parasitic capacitance becomes a significant portion of the total gate capacitance in deep submicron technology, an accurate compact model is required to predict the circuits performance precisely. In LDD (lightly doped drain) technology, the overlap capacitance becomes the major fraction of the total gate capacitance when the device is in OFF condition i.e., $V_{GS}=0V$ Moreover, the major industry models that are currently available do not accurately predict the overlap capacitance. In this work, we present an improved compact model to capture the effect of the drain bias on the overlap capacitance. A detailed 2D numerical device simulation is performed to investigate the impact of drain voltage on the overlap capacitance variation of an LDD MOSFET in the “OFF-state”. The proposed model is validated with the TCAD and experimental data and is also implemented in BSIM-BULK, an industry-standard circuit simulation model.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128654011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jaewan Lim, J. Jeong, Junjong Lee, Seunghwan Lee, Sanguk Lee, R. Baek
{"title":"Investigation of Self-Heating Effect in Forksheet FETs for Sub-3-nm Node","authors":"Jaewan Lim, J. Jeong, Junjong Lee, Seunghwan Lee, Sanguk Lee, R. Baek","doi":"10.1109/EDTM55494.2023.10103113","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103113","url":null,"abstract":"Self-heating effect (SHE) in silicon forksheet field-effect transistors (FSFETs) and nanosheet FETs (NSFETs) for sub-3-nm node was analyzed using calibrated TCAD. For SHE investigation, electrical and thermal properties, and reliability were assessed according to channel width $(W_{CH})$. A silicon-nitride wall deteriorated the thermal properties of FSFETs; however, FSFETs were electrically superior to NSFETs. Furthermore, as $W_{CH}$ decreases, FSFETs exhibited lower lattice temperature and more improved reliability than NSFETs. Therefore, these quantitative comparisons revealed FSFETs surpassed NSFETs in terms of SHE.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131960205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhi Gong, Jiajia Chen, C. Jin, Huan Liu, Y. Liu, Xiao Yu, G. Han
{"title":"Atomic-Scale Study on Amorphous ZrO2/TaON Interface for Ferroelectric-Like Insulator Films","authors":"Zhi Gong, Jiajia Chen, C. Jin, Huan Liu, Y. Liu, Xiao Yu, G. Han","doi":"10.1109/EDTM55494.2023.10103014","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103014","url":null,"abstract":"The atomic-scale behaviors of an amorphous (a-) $text{ZrO}_{2}/text{TaON}$ interface are investigated by ab initio calculations. The results indicate a high ion migration barrier at the interface, which contributes to the over-all ferroelectric-like hysteresis of $mathrm{a}-text{ZrO}_{2}$ thin films. This work facilitates further investigations on the mechanisms and performance of ferroelectric-like insulator films which have great potential in the applications of the emerging non-volatile memories, negative capacitance field-effect transistors, neuro-morphic devices, etc.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125384485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Junxiang Hao, Xiaoran Mei, T. Saraya, T. Hiramoto, M. Kobayashi
{"title":"3D NAND Memory Operation of Oxide-Semiconductor Channel FeFETs and the Potential Impact of In-Plane Polarization","authors":"Junxiang Hao, Xiaoran Mei, T. Saraya, T. Hiramoto, M. Kobayashi","doi":"10.1109/EDTM55494.2023.10103035","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103035","url":null,"abstract":"We have explored 3D NAND memory operation of oxide-semiconductor (OS) channel FeFETs by TCAD simulation with a multi-transistor NAND-string model. Key challenges in 3D NAND memory devices, such as (1) pass voltage disturb, (2) interference from adjacent cells, and (3) inhibit operation of unselected bitlines, are addressed. For a target device structure, operation voltages can be optimized to satisfy the requirement of (1)-(3). We have also studied the potential impact of in-plane polarization under the spacer. A comparative study shows that in-plane polarization under the spacer may lead to unexpected characteristics of OS-channel FeFETs in 3D NAND memory operation. This paper will provide insights on the feasibility of 3D NAND FeFETs for high capacity storage memory.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123258232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Variable-Temperature Broadband Noise Characterization of MOSFETs for Cryogenic Electronics: From Room Temperature down to 3 K","authors":"K. Ohmori, S. Amakawa","doi":"10.1109/edtm55494.2023.10103124","DOIUrl":"https://doi.org/10.1109/edtm55494.2023.10103124","url":null,"abstract":"A broadband noise measurement system is newly developed and demonstrated at temperatures between 3 K and 300 K. Using the system, wideband noise spectroscopy (WBNS) from 20 kHz to 500 MHz is carried out for the first time, revealing that shot noise is the dominant white noise down to 3 K. The paper also suggests, by means of WBNS, the possibility of extracting the baseline noise characteristics, which do not include the noise component that varies a great deal from device to device.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121230232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of RF Frequency Bands on the DC and Large Signal Reliability of a 45nm RFSOI NFET based Power Amplifier Cell","authors":"Aarti Rathi, P. Srinivasan, A. Dixit","doi":"10.1109/EDTM55494.2023.10102985","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10102985","url":null,"abstract":"In this work we highlight the impact of RF frequency on the DC and large signal reliability performance of a single nFET based power-amplifier (PA) cell for three different frequency bands, e.g., Ku, K, and Ka. We observe that the overall performance of the PA cell is superior in the Ka-band but the performance degradation due to reliability mechanisms is also more in this band. The impact of large-signal stress is high when PA is stressed in compression or near the P1dB region. This holds true for all frequency bands investigated in this work.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126978491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiuyang Yuan, Y. Miyamura, S. Nakano, W. Saito, S. Nishizawa
{"title":"The Study of Dislocation Propagation in Si Wafer during IGBT High Thermal Budget Process","authors":"Jiuyang Yuan, Y. Miyamura, S. Nakano, W. Saito, S. Nishizawa","doi":"10.1109/EDTM55494.2023.10103031","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103031","url":null,"abstract":"There are several thermal budget processes for Si-IGBT fabrication, which sometimes cause dislocation propagation. The dislocation propagation depends on temperature and time of the process. In this paper, we analyzed the dislocation propagation in Si wafer during Si-IGBT fabrication process. We also calculated the dislocation density during diffusion process with several temperatures and times, and we confirmed that the lower temperature process causes the smaller dislocation propagation which may carry out the good device performance.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"591 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132615176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Study of High Voltage NMOSFET degradation for NAND HVSW circuit","authors":"Young Gon Lee, Sang Ho Lee, Sung-Kye Park","doi":"10.1109/EDTM55494.2023.10102958","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10102958","url":null,"abstract":"Reliabilities of high voltage transistors has become a major concern for NAND tech scaling. In this work, we investigate reliabilities of HVN transistors. When a high bias stress was applied, large degradation of HVN transistors has been observed. This degradation has been attributed to electron injection with high energy by FN stress. We have found that the Vt shift of HVN causes malfunction of the circuit operation, and we have suggested the fail criteria of HVN for precise evaluation.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133351199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}