Stability and Performance Optimization of 6T SRAM Cell at Cryogenic Temperature

Abstract

Cryogenic on-chip memory is viable for obtaining high-performance computing (HPC) or power reduction. Cryogenic SRAM (Cryo-SRAM) with low threshold voltage (LVT) design at reduced supply voltage (VDD) gets the maximized speed-power gain thanks to the steep subthreshold slope (SS) of cryo-CMOS. However, SRAM with LVT design at 77K may suffer the stability issue. This work demonstrates the optimized threshold voltage design for 6T cryo-SRAM. Compared to the SRAM with LVT design at 77K, the optimized 6T cryo-SRAM cells improve the read and hold static noise margin by 25% and 12%, respectively. Moreover, the optimized 6T cryo-SRAM preserves the speed-power advantages compared to 300K 6T SRAM with standard threshold voltage (SVT) design. The optimized 6T cryo-SRAMs with fast speed and superior stability could be promising candidates for HPC applications.