3D NAND Memory Operation of Oxide-Semiconductor Channel FeFETs and the Potential Impact of In-Plane Polarization

Abstract

We have explored 3D NAND memory operation of oxide-semiconductor (OS) channel FeFETs by TCAD simulation with a multi-transistor NAND-string model. Key challenges in 3D NAND memory devices, such as (1) pass voltage disturb, (2) interference from adjacent cells, and (3) inhibit operation of unselected bitlines, are addressed. For a target device structure, operation voltages can be optimized to satisfy the requirement of (1)-(3). We have also studied the potential impact of in-plane polarization under the spacer. A comparative study shows that in-plane polarization under the spacer may lead to unexpected characteristics of OS-channel FeFETs in 3D NAND memory operation. This paper will provide insights on the feasibility of 3D NAND FeFETs for high capacity storage memory.