Analysis and Modeling of OFF-State Capacitance in LDD MOSFETs

Since the parasitic capacitance becomes a significant portion of the total gate capacitance in deep submicron technology, an accurate compact model is required to predict the circuits performance precisely. In LDD (lightly doped drain) technology, the overlap capacitance becomes the major fraction of the total gate capacitance when the device is in OFF condition i.e., $V_{GS}=0V$ Moreover, the major industry models that are currently available do not accurately predict the overlap capacitance. In this work, we present an improved compact model to capture the effect of the drain bias on the overlap capacitance. A detailed 2D numerical device simulation is performed to investigate the impact of drain voltage on the overlap capacitance variation of an LDD MOSFET in the “OFF-state”. The proposed model is validated with the TCAD and experimental data and is also implemented in BSIM-BULK, an industry-standard circuit simulation model.