2020 IEEE International Electron Devices Meeting (IEDM)最新文献_第10页

Coupler characterization of superconducting transmons qubits for cross-resonance gate 交叉共振门超导传输量子比特的耦合器特性

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371955

H. Paik, S. Srinivasan, S. Rosenblatt, J. Chavez-Garcia, D. Bogorin, O. Jinka, G. Keefe, Dongbing Shao, J. Yau, M. Brink, J. Chow

引用次数: 3

Cryo-CMOS Compact Modeling Cryo-CMOS紧凑建模

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371894

C. Enz, A. Beckers, F. Jazaeri

引用次数: 13

Staggered Metallization with Air gaps for Independently Tuned Interconnect Resistance and Capacitance 具有气隙的交错金属化，用于独立调谐互连电阻和电容

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371946

Kevin L. Lin, M. Anders, R. Bristol, M. Christenson, G. Elbaz, B. Holybee, Himanshu Kaul, M. Kobrinsky, R. Krishnamurthy, M. Reshotko, H. Yoo

引用次数: 1

Lg = 19 nm In0.8Ga0.2As composite-channel HEMTs with fT = 738 GHz and fmax = 492 GHz 在0.8 ga0.2 as复合通道hemt中，Lg = 19 nm, fT = 738 GHz, fmax = 492 GHz

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9372070

Hyeon-Bhin Jo, Seung-Won Yun, Jun-Gyu Kim, D. Yun, I. Lee, Daehyun Kim, Tae-Woo Kim, Sang-Kuk Kim, J. Yun, T.E. Kim, T. Tsutsumi, H. Sugiyama, H. Matsuzaki

{"title":"Lg = 19 nm In0.8Ga0.2As composite-channel HEMTs with fT = 738 GHz and fmax = 492 GHz","authors":"Hyeon-Bhin Jo, Seung-Won Yun, Jun-Gyu Kim, D. Yun, I. Lee, Daehyun Kim, Tae-Woo Kim, Sang-Kuk Kim, J. Yun, T.E. Kim, T. Tsutsumi, H. Sugiyama, H. Matsuzaki","doi":"10.1109/IEDM13553.2020.9372070","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372070","url":null,"abstract":"We present L<inf>g</inf> = 19 nm In<inf>0.8</inf>Ga<inf>0.2</inf>As composite-channel high-electron mobility transistors (HEMTs) with outstanding DC and high-frequency characteristics. We adopted a composite-channel design with an In<inf>0.8</inf>Ga<inf>0.2</inf>As core layer that led to superior carrier transport properties. The device with L<inf>g</inf> = 19 nm displayed an excellent combination of R<inf>ON</inf> = 271 Ω-μm, g<inf>m_max</inf> = 2.5 mS/μm and f<inf>T</inf>/f<inf>max</inf> = 738/492 GHz. To understand the physical origin of such an excellent combination of DC and RF responses, we analyzed the effective mobility (μ<inf>n_eff</inf>) and delay time for both long- and short-L<inf>g</inf> devices, revealing a very high μ<inf>n_eff</inf> value of 13,200 cm<sup>2</sup>/V•s and an average velocity under the gate (v<inf>avg</inf>) of 6.2 × 10<sup>7</sup> cm/s. We also studied the impact of the gate-to-source spacing (L<inf>GS</inf>) and the electrostatic integrity of the device, finding that a reduction of L<inf>GS</inf> less than 0.6 μm was of little use in improving g<inf>m_max</inf> and f<inf>T</inf>. Additionally, the intrinsic output conductance (g<inf>o_int</inf>) had an important impact on f<inf>T</inf> in short-L<inf>g</inf> HEMTs.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130859628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Vertical Gate-All-Around Tunnel FETs Using InGaAs Nanowire/Si with Core-Multishell Structure 基于InGaAs纳米线/硅的垂直栅-全隧道场效应管

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371991

K. Tomioka, H. Gamo, J. Motohisa, T. Fukui

引用次数: 2

First Demonstration of OxRRAM Integration on 14nm FinFet Platform and Scaling Potential Analysis towards Sub-10nm Node 14nm FinFet平台上OxRRAM集成的首次演示及亚10nm节点的缩放潜力分析

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371971

Xiaoxin Xu, Jie Yu, Tiancheng Gong, Jianguo Yang, Jiahao Yin, Da Nian Dong, Q. Luo, Jing Liu, Zhaoan Yu, Qi Liu, H. Lv, Ming Liu

引用次数: 10

Cryo-CMOS Interfaces for Large-Scale Quantum Computers 大规模量子计算机的Cryo-CMOS接口

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9372075

F. Sebastiano, J. V. van Dijk, P. Hart, B. Patra, J. van Staveren, X. Xue, C. G. Almudever, G. Scappucci, M. Veldhorst, L. Vandersypen, A. Vladimirescu, S. Pellerano, M. Babaie, E. Charbon

引用次数: 8

GaN Power ICs: Reviewing Strengths, Gaps, and Future Directions GaN功率ic:回顾优势、差距与未来方向

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371918

O. Trescases, S. Murray, W. L. Jiang, M. S. Zaman

引用次数: 16

Thin-Film Transistor Platform for Electrophysiological and Electrochemical Characterization of Biological Cells 生物细胞电生理和电化学表征的薄膜晶体管平台

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9372043

A. Eiler, Pierre-Marie Faure, J. Sugita, S. Ihida, D. Zhu, Y. Sakai, K. Fujiu, K. Komori, H. Toshiyoshi, A. Tixier-Mita

引用次数: 2

Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance 安全的3D CMOS芯片堆栈与后埋金属供电网络分布式去耦电容

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9372073

H. Sonoda, Kazuki Monta, Takaaki Okidono, Y. Araga, N. Watanabe, H. Shimamoto, K. Kikuchi, N. Miura, Takuji Miki, M. Nagata

{"title":"Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance","authors":"H. Sonoda, Kazuki Monta, Takaaki Okidono, Y. Araga, N. Watanabe, H. Shimamoto, K. Kikuchi, N. Miura, Takuji Miki, M. Nagata","doi":"10.1109/IEDM13553.2020.9372073","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372073","url":null,"abstract":"Secure three-dimensional (3D) CMOS chip stacks with backside buried metal (BBM) routing provide low series impedance and high decoupling capability in a power delivery network (PDN), thanks to its distributed capacitances over a full-chip backside area. The Si demonstrator with cryptographic functionality was fabricated in a 0.13-µm CMOS technology with post-Si wafer-level BBM Cu processing with 10 µm, 15 µm and 35 µm of thickness, line width and space, along with through Si vias (TSVs) with 10 µm and 40 µm of diameter and depth, respectively. The capacitance of 0.18 nF/mm2 in the effective backside area of 71 mm2 suppressed dynamic IR drops in 10% and 59% for the single chip and four chip stack samples, respectively, during the operation of a 3.9M-gate crypto core at 30 MHz. This was confirmed by on-chip power noise monitoring. The 3D BBM PDN also effectively reduces power side channel information leakage, which is evaluated by 8x increase in the number of externally observed electromagnetic (EM) noise waveforms to attain the t-test value of larger than 4.5 if we assume the statistically effective correlation between EM noise emission and secret information in the crypto core.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114428751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5