2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第4页

Performance sensor for tolerance and predictive detection of delay-faults 延迟故障公差和预测检测性能传感器

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962092

J. Semião, David Saraiva, C. Leong, A. Romão, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira

{"title":"Performance sensor for tolerance and predictive detection of delay-faults","authors":"J. Semião, David Saraiva, C. Leong, A. Romão, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira","doi":"10.1109/DFT.2014.6962092","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962092","url":null,"abstract":"This paper presents the Scout Flip-Flop, a new performance Sensor for toleranCe and predictive detectiOn of delay-faUlTs in synchronous digital circuits. The sensor is based on a new master-slave Flip-Flop (FF), the Scout FF, with built-in functionality to locally (inside the FF) create two distinct guard-band windows: (1) a tolerance window, to increase tolerance to late transitions, making the Scout's master latch transparent during an additional predefined period after the clock trigger; and (2) a detection window, which starts before the clock edge trigger and persists during the tolerance window, to inform that performance and circuit functionality is at risk. When a PVTA (Process, power-supply Voltage, Temperature and Aging) variation occurs, circuit performance is affected and a delay-fault may occur. Hence, the existence of a tolerance window, introduces an extra time-slack by borrowing time from subsequent clock cycles. Moreover, as the predictive-error detection window starts prior to the clock edge trigger, it provides an additional safety margin and may be used to trigger corrective actions before real error occurrence, such as clock frequency reduction. Both tolerance and detection windows are defined by design and are sensitive to performance errors, increasing its size in worst PVTA conditions. Extensive SPICE simulations allowed characterizing the new flip-flop and simulation results are presented for 65nm CMOS technology, using Berkeley Predictive Technology Models (PTM), showing Scout's effectiveness on tolerance and predictive error detection.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125655225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Estimating the effect of single-event upsets on microprocessors 估计单事件扰动对微处理器的影响

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962059

C. Constantinescu, Srini Krishnamoorthy, Tuyen Nguyen

引用次数: 3

Automated formal approach for debugging dividers using dynamic specification 使用动态规范调试分压器的自动正式方法

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962068

M. Haghbayan, B. Alizadeh, A. Rahmani, P. Liljeberg, H. Tenhunen

引用次数: 4

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch 采用内置自校准技术的12位32MS/s SAR ADC，可最大限度地减少电容失配

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962078

In-Seok Jung, Yong-Bin Kim

{"title":"A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch","authors":"In-Seok Jung, Yong-Bin Kim","doi":"10.1109/DFT.2014.6962078","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962078","url":null,"abstract":"This paper presents a low-power 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input with a novel Built-in Self Calibration (BiSC) feature to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as fore-ground operation so that low power consumption is achieved. Consequently, the mismatch error of the DAC can be minimized and the SAR based ADC operates without any extra power dissipation for the circuitry of self calibration during normal operation. The prototype was designed using 0.13μm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.2 dB and consumes 3.57 mW with 1.2V supply voltage and sampling rate of 32 MS/s. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 45% and 51%, respectively.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"6 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128413123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Design and implementation of a self-healing processor on SRAM-based FPGAs 基于sram的fpga自愈处理器的设计与实现

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962076

M. Psarakis, A. Vavousis, C. Bolchini, A. Miele

引用次数: 15

Machine learning-based techniques for incremental functional diagnosis: A comparative analysis 基于机器学习的增量功能诊断技术:比较分析

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962064

C. Bolchini, Luca Cassano

引用次数: 6

GPGPUs ECC efficiency and efficacy gpgpu的ECC效率和功效

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962085

Daniel Oliveira, P. Rech, L. Pilla, P. Navaux, L. Carro

引用次数: 18

Domino effect protection on dataflow error detection and recovery 数据流错误检测和恢复的多米诺效应保护

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962087

Tiago A. O. Alves, L. A. J. Marzulo, S. Kundu, F. França

引用次数: 2

Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs 基于sram的fpga中不同三模冗余降低FIT

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962070

L. Tambara, F. Kastensmidt, P. Rech, C. Frost

引用次数: 4

Protecting cryptographic hardware against malicious attacks by nonlinear robust codes 利用非线性鲁棒代码保护加密硬件免受恶意攻击

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962084

V. Tomashevich, Yaara Neumeier, Raghavan Kumar, O. Keren, I. Polian

引用次数: 22