基于sram的fpga中不同三模冗余降低FIT

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI:10.1109/DFT.2014.6962070

L. Tambara, F. Kastensmidt, P. Rech, C. Frost

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引用次数: 4

摘要

本文探讨了设计分集冗余的概念应用于基于sram的fpga，以降低故障率。32位RISC处理器MIPS采用了粗粒三模冗余(TMR)和多元模冗余(DTMR)两种保护方式。在中子通量辐射下的实验结果表明，与标准MIPS相比，DTMR可以使系统的时间失效(FIT)降低40%，而粗增益TMR只能使系统的时间失效(FIT)降低10%。

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Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs

This paper explores the concept of Design Diversity Redundancy applied to SRAM-based FPGAs as a proposal to decrease failure rate. A 32-bit RISC processor MIPS was protected by coarse grain Triple Modular Redundancy (TMR) and by Diverse TMR (DTMR). Experimental results under neutron flux radiation show that DTMR can reduce in 40% the Failure in Time (FIT) of a system when compared to the standard MIPS while the coarse gain TMR could reduce the FIT in only 10%.

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来源期刊

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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