2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献

Exploration of system availability during software-based self-testing in many-core systems under test latency constraints 在测试延迟约束下的多核系统中基于软件的自测试期间系统可用性的探索

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962088

M. Skitsas, C. Nicopoulos, M. Michael

{"title":"Exploration of system availability during software-based self-testing in many-core systems under test latency constraints","authors":"M. Skitsas, C. Nicopoulos, M. Michael","doi":"10.1109/DFT.2014.6962088","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962088","url":null,"abstract":"As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, we investigate the relation between system test latency and testtime overhead in multi-/many-core systems with shared LastLevel Cache (LLC) for periodic Software-Based Self-Testing (SBST), under different test scheduling policies. The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system testing session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relation between the two test measures; as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for running normal workloads. Under given system test latency constraints, which should be utilized in order to be able to control system recovery time in the event of an error detection, our exploration framework identifies the scheduling policy under which overall test time overhead is minimized and, hence, system availability is maximized. Without any loss of generality, a 16-core system is explored in a full-system, execution-driven simulation framework running multi-threaded PARSEC workloads [1].","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115647409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Unifying scan compression 统一扫描压缩

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962079

Swapnil Bahl, Shrey Rungta, Shray Khullar, R. Kapur, A. Chandra, S. Talluto, Pramod Notiyath, Ajay Rajagopalan

引用次数: 4

SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs 在现代soc中访问嵌入式传感器的综合机制

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962097

M. He, M. Tehranipoor

引用次数: 8

CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly CSST:防止由不可信的代工和组装分发未经许可和被拒绝的ic

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962096

Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, M. Tehranipoor

{"title":"CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly","authors":"Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, M. Tehranipoor","doi":"10.1109/DFT.2014.6962096","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962096","url":null,"abstract":"The globalization of the semiconductor design and fabrication industry (also known as the horizontal business model) has led to many well-documented issues associated with untrusted foundries and assemblies, including IC overproduction, cloning, and the shipping of improperly or insufficiently tested chips. Besides the loss in profits to Intellectual Property (IP) owners, such chips entering the supply chain can have catastrophic consequences for critical applications. We propose a new Secure Split-Test (SST) scheme called the Connecticut SST (CSST) in which the IP owner takes full control over testing. In CSST, each chip and its scan chains are locked during testing, and only the IP owner can interpret the locked test results and unlock passing chips. The new SST can prevent overproduced, defective, and cloned chips from reaching the supply chain. The proposed method considerably simplifies the communication required between the foundry/assembly and the IP owner compared to the original version of the SST. The results demonstrate that our new technique is more secure than the original and has lower communication overheads.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115858001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

Reliability estimation at block-level granularity of spin-transfer-torque MRAMs 基于块级粒度的自旋-传递-扭矩mram可靠性估计

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962093

S. Carlo, Marco Indaco, P. Prinetto, E. Vatajelu, R. Rodríguez-Montañés, J. Figueras

引用次数: 1

Fault tolerant and highly adaptive routing for 2D NoCs 二维noc的容错和高自适应路由

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962100

Manoj Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, M. Ebrahimi, Mark Zwolinski

{"title":"Fault tolerant and highly adaptive routing for 2D NoCs","authors":"Manoj Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, M. Ebrahimi, Mark Zwolinski","doi":"10.1109/DFT.2014.6962100","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962100","url":null,"abstract":"Networks-on-Chip (NoCs) are emerging as a promising communication paradigm to overcome bottleneck of traditional bus-based interconnects for current microarchitectures (MCSoC and CMP). One of the known current problems in NoC routing is the use of acyclic Channel Dependency Graph (CDG) for deadlock freedom. This requirement forces certain routing turns to be prohibited, thus, reducing the degree of adaptiveness. In this paper, we propose a novel non-minimal turn model which allows cycles in CDG provided that Extended Channel Dependency Graph (ECDG) remains acyclic. The proposed turn model reduces number of restrictions on routing turns, hence able to provide path diversity through additional minimal and non-minimal routes between source and destination. We also develop a fault tolerant and congestion-aware routing algorithm based on the proposed turn model to demonstrate the effectiveness. In this algorithm, a non-minimal route is used only when links in minimal routes are congested or faulty. Average performance gain of the proposed method is up to 26% across all selected benchmarks when compared with DRFT and 12% when compared with LEAR for 7 × 7 mesh.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129629642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A runtime manager for gracefully degrading SoCs 用于优雅地降级soc的运行时管理器

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962106

S. Tzilis, I. Sourdis

{"title":"A runtime manager for gracefully degrading SoCs","authors":"S. Tzilis, I. Sourdis","doi":"10.1109/DFT.2014.6962106","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962106","url":null,"abstract":"The increasing number of transistors integrated on a single chip comes with the blessing of raw computational power and the curse of susceptibility to various kinds of faults. On top of increased defect densities, wearout effects mean that the testing verdict at fabrication time cannot be trusted throughout the chip lifetime. However, extra computational power presents the opportunity to build gracefully degrading MPSoCs. Re-configurable components and flexible workloads, along with runtime support, enable MPSoCs to deal with permanent faults degrading one or more system aspects, such as performance, energy efficiency and delivered functionality, instead of failing. In this manner, chip life is prolonged and safety is increased. In this work Graceful Degradation (GD) is formulated as an optimization problem in the context of MPSoCs. As such, its possible solutions can be evaluated in a parameterizable and consistent manner. An attempt at a runtime solution for a heterogeneous 4-core SoC is made and the resulting GD manager is evaluated in terms of speed and accuracy, with a use case combining essential automotive tasks and non-essential additional features. On average, it is found to produce a solution 89% as good as the optimal, in 4.3μsec running on one core of a common modern CPU.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130639163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs 基于Xilinx sram的fpga上快速单事件故障仿真的故障注入方法和基础结构

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962073

S. Carlo, P. Prinetto, Daniele Rolfo, Pascal Trotta

引用次数: 31

An instance-based SER analysis in the presence of PVTA variations 在存在PVTA变化的情况下，基于实例的SER分析

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962081

Bahareh J. Farahani, S. Safari

引用次数: 4

Security methods in fault tolerant modified line graph based networks 基于容错修正线图的网络安全方法

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962104

Prashant D. Joshi, S. Hamdioui

引用次数: 1