2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第2页

Using memristor state change behavior to identify faults in photovoltaic arrays 利用忆阻器状态变化行为识别光伏阵列故障

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962094

J. Mathew, M. Ottavi, Yunfan Yang, D. Pradhan

引用次数: 4

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance 耐单事件干扰(SEU)的非易失性存储单元的设计与分析

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962061

Wei Wei, F. Lombardi, K. Namba

引用次数: 4

Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors 芯片多处理器缓存一致性协议软错误漏洞特征分析

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962071

C. Zheng, Shuai Wang

{"title":"Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors","authors":"C. Zheng, Shuai Wang","doi":"10.1109/DFT.2014.6962071","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962071","url":null,"abstract":"Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and transistor budget, protecting them against soft errors is of paramount importance. Recent research has focused on the characterization and optimization for the reliability of data caches in single-core processors. As the mainstream processors enter the multi-/many-core era, the area share of the on-chip caches keeps increasing, which makes them more vulnerable to soft errors. However, few research work has studied the vulnerability of the on-chip caches in the context of the cache coherence protocols. In this work, we propose to characterize the soft error vulnerability of the L1 data cache in chip-multiprocessors (CMPs) under the influence of different cache coherence protocols. This study aims to provide insights into cache vulnerability behaviors in CMPs as well as guidance in designing reliable cache coherence protocols. Furthermore, an early-invalidation scheme is proposed to reduce the overall vulnerability factor of the data caches in CMPs. Benchmarking is carried out to showcase the effectiveness of our approach.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114486939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A data recomputation approach for reliability improvement of scratchpad memory in embedded systems 一种提高嵌入式系统刮本存储器可靠性的数据重计算方法

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962091

H. Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, S. Miremadi

{"title":"A data recomputation approach for reliability improvement of scratchpad memory in embedded systems","authors":"H. Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, S. Miremadi","doi":"10.1109/DFT.2014.6962091","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962091","url":null,"abstract":"Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and minimum overheads. This proposed data recomputation algorithm recomputes the correct value whenever an error is detected in the SPM. The simulation results show that the proposed algorithm significantly reduces the vulnerability of SPM from 91.7% to 8.4%. Moreover, the proposed algorithm imposes no area overhead and no hardware modification, meanwhile its performance overhead is less than 1%.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131453740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Rescuing healthy cores against disabled routers 对禁用路由器抢救健康核心

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962086

M. Ebrahimi, Junshi Wang, Letian Huang, M. Daneshtalab, A. Jantsch

引用次数: 6

A system-level scheme for resistance drift tolerance of a multilevel phase change memory 一种多电平相变存储器电阻漂移容限的系统级方案

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962060

P. Junsangsri, Jie Han, F. Lombardi

引用次数: 7

TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip 三维片上网络的tsv - tsv感应耦合感知编码方案

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962067

Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, N. Bagherzadeh

引用次数: 11

Scheduling algorithm in datapath synthesis for long duration transient fault tolerance 基于长时间暂态容错的数据路径综合调度算法

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962062

T. Iwagaki, Tatsuya Nakaso, R. Ohkubo, H. Ichihara, Tomoo Inoue

引用次数: 9

Diagnosis of segment delay defects with current sensing 基于电流传感的分段延迟缺陷诊断

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962101

Wisam Aljubouri, Ahish Mysore Somashekar, T. Haniotakis, S. Tragoudas

引用次数: 3

Characterization of data retention faults in DRAM devices DRAM设备中数据保留故障的表征

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962069

Angelo Bacchini, M. Rovatti, G. Furano, M. Ottavi

引用次数: 16