2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第3页

Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs fpga上容错电路结构的解析可靠性评估

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962108

J. Anwer, M. Platzner

{"title":"Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs","authors":"J. Anwer, M. Platzner","doi":"10.1109/DFT.2014.6962108","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962108","url":null,"abstract":"With increasing error-proneness of nano-circuits, a number of fault-tolerance approaches are presented in the literature to enhance circuit reliability. The evaluation of the effectiveness of fault-tolerant circuit structures remains a challenge. An analytical model is required to provide exact figures of reliability of a circuit design, to be able to locate error-sensitive parts of the circuit as well as to compare different fault-tolerance approaches. At the logic layer, probabilistic approaches exist that provide such measures of circuit reliability, but they do not consider the reliability-enhancement effect of fault-tolerant circuit structures. Furthermore, these approaches are often not applicable for large circuits and their complexity hinders the development of generic simulation tools. In this paper we combine the Boolean difference error calculator (BDEC), a previous probabilistic reliability model for hardware designs, with a reliability model for fault-tolerant circuit structures. As a result we are able to study the reliability of fault-tolerant circuit structures at the logic layer. We focus on fault-tolerant circuits to be implemented in FPGAs and show how to extend our combined model from combinational to sequential circuits. For analyzing larger circuits, we develop a MATLAB-based tool utilizing BDEC. With this tool, we perform a variability analysis of different input parameters, such as logic component, input and voter error probabilities, to observe their single and joint effect on the circuit reliability. Our analyses show that circuit reliability depends strongly on the circuit structure due to error-masking effects of components on each other. Moreover, the benefit of redundancy can be obtained up to a certain threshold of component, input and voter error probabilities though the voter reliability has the strongest impact on overall circuit reliability.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129394523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Improved correction for hot pixels in digital imagers 改进了对数字成像仪中的热像素的校正

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962103

G. Chapman, Rohit Thomas, Rahul Thomas, I. Koren, Z. Koren

引用次数: 2

Energy-efficient concurrent testing approach for many-core systems in the dark silicon age 暗硅时代多核系统的节能并行测试方法

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962075

M. Haghbayan, A. Rahmani, P. Liljeberg, J. Plosila, H. Tenhunen

{"title":"Energy-efficient concurrent testing approach for many-core systems in the dark silicon age","authors":"M. Haghbayan, A. Rahmani, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1109/DFT.2014.6962075","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962075","url":null,"abstract":"Dark Silicon issue stresses that a fraction of silicon chip being able to switch in a full frequency is dropping and designers will soon face a growing underutilization inherent in future technology scaling. On the other hand, by reducing the transistor sizes, susceptibility to internal defects increases and large range of defects such as aging or transient faults will be shown up more frequently. In this paper, we propose an online concurrent test scheduling approach for the fraction of chip that cannot be utilized due to the restricted utilization wall. Dynamic voltage and frequency scaling including near-threshold operation is utilized in order to maximize the concurrency of the online testing process under the constant power. As the dark area of the system is dynamic and reshapes at a runtime, our approach dynamically tests unused cores in a runtime to provided tested cores for upcoming application and hence enhance system reliability. Empirical results show that our proposed concurrent testing approach using dynamic voltage and frequency scaling (DVFS) improves the overall test throughput by over 250% compared to the state-of-the-art dark silicon aware online testing approaches under the same power budget.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121583805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A heuristic path selection method for small delay defects test 小延迟缺陷检测的启发式路径选择方法

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962082

Paniz Foroutan, M. Kamal, Z. Navabi

引用次数: 3

Aging analysis for recycled FPGA detection 回收FPGA检测的老化分析

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962099

H. Dogan, Domenic Forte, M. Tehranipoor

{"title":"Aging analysis for recycled FPGA detection","authors":"H. Dogan, Domenic Forte, M. Tehranipoor","doi":"10.1109/DFT.2014.6962099","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962099","url":null,"abstract":"The counterfeit electronic component industry continues to threaten the security and reliability of systems by infiltrating recycled components into the supply chain. With the increased use of FPGAs in critical systems, recycled FPGAs cause significant concerns for government and industry. In this paper, we propose a two phase detection approach to differentiate recycled (used) FPGAs from new ones. Both approaches rely on machine learning via support vector machines (SVM) for classification. The first phase examines suspect FPGAs “as is” while the second phase requires some accelerated aging. To be more specific, Phase I detects recycled FPGAs by comparing the frequencies of ring oscillators (ROs) distributed on the FPGAs against a golden model. Experimental results on Xilinx FPGAs show that Phase I can correctly classify 8 out of 20 FPGAs under test. However, Phase I fails to detect FPGAs at fast corners and with lesser prior usage. Phase II is then used to compliment Phase I and overcome its limitations. The second phase performs a short aging step on the suspect FPGAs and exploits the aging speed reduction (due to prior usage) to cover the cases missed by Phase I. In our silicon results, Phase II detects all the fresh and recycled FPGAs correctly.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133387206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 67

A probabilistic analysis of resilient reconfigurable designs 弹性可重构设计的概率分析

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962074

A. Malek, S. Tzilis, D. Khan, I. Sourdis, Georgios Smaragdos, C. Strydis

{"title":"A probabilistic analysis of resilient reconfigurable designs","authors":"A. Malek, S. Tzilis, D. Khan, I. Sourdis, Georgios Smaragdos, C. Strydis","doi":"10.1109/DFT.2014.6962074","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962074","url":null,"abstract":"Reconfigurable hardware can be employed to tolerate permanent faults. Hardware components comprising a System-on-Chip can be partitioned into a handful of substitutable units interconnected with reconfigurable wires to allow isolation and replacement of faulty parts. This paper offers a probabilistic analysis of reconfigurable designs estimating for different fault densities the average number of fault-free components that can be constructed as well as the probability to guarantee a particular availability of components. Considering the area overheads of reconfigurability, we evaluate the resilience of various reconfigurable designs with different granularities. Based on this analysis, we conduct a comprehensive design-space exploration to identify the granularity mixes that maximize the fault-tolerance of a system. Our findings reveal that mixing fine-grain logic with a coarse-grain sparing approach tolerates up to 3× more permanent faults than component redundancy and 2× more than any other purely coarse-grain solution. Component redundancy is preferable at low fault densities, while coarse-grain and mixed-grain reconfigurability maximize availability at medium and high fault densities, respectively.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability 基于氧化物的阻性RAM:开/关电阻分析与电路可变性

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962107

H. Aziza, H. Ayari, S. Onkaraiah, J. Portal, M. Moreau, M. Bocquet

引用次数: 1

Exploiting Intel TSX for fault-tolerant execution in safety-critical systems 利用Intel TSX在安全关键系统中实现容错执行

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962083

Florian Haas, Sebastian Weis, Stefan Metzlaff, T. Ungerer

引用次数: 5

Fault injection in the process descriptor of a Unix-based operating system 基于unix的操作系统的进程描述符中的错误注入

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962080

B. Montrucchio, M. Rebaudengo, A. Velasco

引用次数: 7

Artificial intelligence based task mapping and pipelined scheduling for checkpointing on real time systems with imperfect fault detection 基于人工智能的任务映射和流水线调度用于不完全故障检测的实时系统的检查点

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962066

Anup Das, Akash Kumar, B. Veeravalli

{"title":"Artificial intelligence based task mapping and pipelined scheduling for checkpointing on real time systems with imperfect fault detection","authors":"Anup Das, Akash Kumar, B. Veeravalli","doi":"10.1109/DFT.2014.6962066","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962066","url":null,"abstract":"Fault-tolerance is emerging as one of the important optimization objectives for designs in deep submicron technology nodes. This paper proposes a technique of application mapping and scheduling with checkpointing on a multiprocessor system to maximize the reliability considering transient faults. The proposed model incorporates checkpoints with imperfect fault detection probability, and pipelined execution and cyclic dependency associated with multimedia applications. This is solved using an Artificial Intelligence technique known as Particle Swarm Optimization to determine the number of checkpoints of every task of the application that maximizes the confidence of the output. The proposed approach is validated experimentally with synthetic and real-life application graphs. Results demonstrate the proposed technique improves the probability of correct result by an average 15% with imperfect fault detection. Additionally, even with 100% fault detection, the proposed technique is able to achieve better results (25% higher confidence) as compared to the existing fault-tolerant techniques.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114418471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2