2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第5页

Preemptive multi-bit IJTAG testing with reconfigurable infrastructure 具有可重构基础结构的抢占式多比特IJTAG测试

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962089

S. Keshavarz, Amirreza Nekooei, Z. Navabi

引用次数: 5

A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA 内置校准系统与减少FFT引擎，用于低功率LNA的线性优化

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-11-24 DOI: 10.1109/DFT.2014.6962077

Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, M. Onabajo, Yong-Bin Kim

{"title":"A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA","authors":"Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, M. Onabajo, Yong-Bin Kim","doi":"10.1109/DFT.2014.6962077","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962077","url":null,"abstract":"A digital built-in calibration (BIC) system with a power and area optimized on-chip fast Fourier transform (FFT) engine is presented to automatically adjust the linearity of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. To compensate the low gain of an envelope detector and to enhance reliability of spectral analysis, an RF amplifier is designed between the LNA and the envelope detector. The output of the envelope detector is digitized before the spectrum calculation with the integrated FFT for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter model, and digital blocks operating with a 51.2MHz clock frequency. The total time required for calibration is 485μs including delays of 1.2μs to allow settling of the LNA output after capacitor array changes for tuning. In order to validate the proposed BIC technique with device mismatch effects, Monte Carlo simulations are performed with the same condition at transient simulations, where the results are well matched with the optimum IM3 component values calculated at the output node of LNA. The digital blocks were implemented using a standard 0.13μm CMOS technology.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116817159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Triggering Trojans in SRAM circuits with X-propagation 基于x传播的SRAM电路中触发木马

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-10-01 DOI: 10.1109/DFT.2014.6962105

Senwen Kan, Jennifer Dworak

引用次数: 6

Shortest path reduction in a class of uniform fault tolerant networks 一类一致容错网络的最短路径约简

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-10-01 DOI: 10.1109/DFT.2014.6962102

Prashant D. Joshi, S. Hamdioui

引用次数: 1

Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults 基于永久故障重构技术的动态调度超标量处理器诊断自检

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-10-01 DOI: 10.1109/DFT.2014.6962072

Mario Schölzel, T. Koal, H. Vierhaus

{"title":"Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults","authors":"Mario Schölzel, T. Koal, H. Vierhaus","doi":"10.1109/DFT.2014.6962072","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962072","url":null,"abstract":"Diagnostic self-test in-the-field for processors becomes mandatory for reconfigurable fault tolerant processor-based systems. Software-based self-test techniques are well suited for providing a pass/fail test in-the-field. However, a diagnostic result for dynamically scheduled processors is usually not obtained by these tests, because the software has no control about the used components of the processor during the execution of the test program. This paper provides a concept for a simple hardware extension of a dynamically scheduled processor, such that the test program gets control about the resource usage. With this technique, for the first time, it becomes feasible to perform a diagnostic software-based self-test for dynamically scheduled processors that is able to distinguish between faults in various components of the processor. In particular, the instruction queue, reservation stations, functional units, and reorder buffer are taken into account. Thereby, the hardware overhead for self-test and reconfiguration is less than 6%.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123285316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Power droop reduction during Launch-On-Shift scan-based logic BIST 在基于换挡发射扫描的逻辑BIST中降低功耗

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-10-01 DOI: 10.1109/DFT.2014.6962063

M. Omaña, Daniele Rossi, Edda Beniamino, C. Metra, C. Tirumurti, R. Galivanche

{"title":"Power droop reduction during Launch-On-Shift scan-based logic BIST","authors":"M. Omaña, Daniele Rossi, Edda Beniamino, C. Metra, C. Tirumurti, R. Galivanche","doi":"10.1109/DFT.2014.6962063","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962063","url":null,"abstract":"The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be erroneously recognized as presence of delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel approach to reduce PD during at-speed test with scan-based Logic BIST using the Launch-On-Shift scheme. Our approach increases the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, when the test vectors are applied, the activity factor (AF) of the scan chains is reduced by approximately the 50% with respect to conventional scan-based LBIST, with no drawbacks on test length and fault coverage, and at the cost of very limited area overhead. We also show that compared to two recent alternate solutions, our approach features a comparable AF in the scan chains during the application of test vectors, while it requires a significantly lower test time or area overhead.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130284813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems 利用动态局部重构技术对可重构系统中的永久故障进行在线按需测试

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-10-01 DOI: 10.1109/DFT.2014.6962065

D. Sorrenti, D. Cozzi, S. Korf, Luca Cassano, J. Hagemeyer, Mario Porrmann, C. Bernardeschi

引用次数: 4

On the in-field functional testing of decode units in pipelined RISC processors 流水线RISC处理器译码单元的现场功能测试

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-10-01 DOI: 10.1109/DFT.2014.6962090

P. Bernardi, R. Cantoro, Lyl M. Ciganda Brasca, E. Sánchez, M. Reorda, S. D. Luca, Renato Meregalli, A. Sansonetti

引用次数: 22

Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip 基于ieee1500的片上系统安全监控测试基础架构设计

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-10-01 DOI: 10.1109/DFT.2014.6962098

J. Backer, D. Hély, R. Karri

引用次数: 5