一类一致容错网络的最短路径约简

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2014-10-01 DOI:10.1109/DFT.2014.6962102

Prashant D. Joshi, S. Hamdioui

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引用次数: 1

摘要

本文描述了一类使用改进线形图设计的最优容错网络的最短路径确定。适当的节点命名允许在0(log n)步中确定最短路径。这即使在存在节点故障的情况下也适用，没有循环或回溯。网络的延伸保持在理论值可能的最小值1。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Shortest path reduction in a class of uniform fault tolerant networks

Shortest path determination in a class of optimally fault tolerant networks designed using modified line graphs is described here. Appropriate node naming allows the shortest paths to be determined in 0(log n) steps. This is applicable even in the presence of node failures, without loops or backtracking. The stretch of the network is maintained at the theoretically minimum value possible of one.

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2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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