Preemptive multi-bit IJTAG testing with reconfigurable infrastructure

Abstract

Technology scaling, increasing transistor density, and design complexity poses new challenges in testing of digital systems. IJTAG is a new proposed standard to access embedded instruments in a chip. However, with growing complexity of embedded chips, shifting data serially might result in high test application time. In this paper, a preemptive parallel test scheduling method for IJTAG environment is introduced to reduce test application time while considering maximum power limitation. Furthermore, an architecture is proposed to support fully reconfigurable multi-bit IJTAG architecture that could be changed at runtime. Experimental results show that applying the proposed method for the framework results in test application time reduction in comparison with other existing methods.