H. Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, S. Miremadi
{"title":"一种提高嵌入式系统刮本存储器可靠性的数据重计算方法","authors":"H. Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, S. Miremadi","doi":"10.1109/DFT.2014.6962091","DOIUrl":null,"url":null,"abstract":"Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and minimum overheads. This proposed data recomputation algorithm recomputes the correct value whenever an error is detected in the SPM. The simulation results show that the proposed algorithm significantly reduces the vulnerability of SPM from 91.7% to 8.4%. Moreover, the proposed algorithm imposes no area overhead and no hardware modification, meanwhile its performance overhead is less than 1%.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"A data recomputation approach for reliability improvement of scratchpad memory in embedded systems\",\"authors\":\"H. Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, S. Miremadi\",\"doi\":\"10.1109/DFT.2014.6962091\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and minimum overheads. This proposed data recomputation algorithm recomputes the correct value whenever an error is detected in the SPM. The simulation results show that the proposed algorithm significantly reduces the vulnerability of SPM from 91.7% to 8.4%. Moreover, the proposed algorithm imposes no area overhead and no hardware modification, meanwhile its performance overhead is less than 1%.\",\"PeriodicalId\":414665,\"journal\":{\"name\":\"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2014.6962091\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2014.6962091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A data recomputation approach for reliability improvement of scratchpad memory in embedded systems
Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and minimum overheads. This proposed data recomputation algorithm recomputes the correct value whenever an error is detected in the SPM. The simulation results show that the proposed algorithm significantly reduces the vulnerability of SPM from 91.7% to 8.4%. Moreover, the proposed algorithm imposes no area overhead and no hardware modification, meanwhile its performance overhead is less than 1%.