Fault tolerant and highly adaptive routing for 2D NoCs

Abstract

Networks-on-Chip (NoCs) are emerging as a promising communication paradigm to overcome bottleneck of traditional bus-based interconnects for current microarchitectures (MCSoC and CMP). One of the known current problems in NoC routing is the use of acyclic Channel Dependency Graph (CDG) for deadlock freedom. This requirement forces certain routing turns to be prohibited, thus, reducing the degree of adaptiveness. In this paper, we propose a novel non-minimal turn model which allows cycles in CDG provided that Extended Channel Dependency Graph (ECDG) remains acyclic. The proposed turn model reduces number of restrictions on routing turns, hence able to provide path diversity through additional minimal and non-minimal routes between source and destination. We also develop a fault tolerant and congestion-aware routing algorithm based on the proposed turn model to demonstrate the effectiveness. In this algorithm, a non-minimal route is used only when links in minimal routes are congested or faulty. Average performance gain of the proposed method is up to 26% across all selected benchmarks when compared with DRFT and 12% when compared with LEAR for 7 × 7 mesh.