Swapnil Bahl, Shrey Rungta, Shray Khullar, R. Kapur, A. Chandra, S. Talluto, Pramod Notiyath, Ajay Rajagopalan
{"title":"统一扫描压缩","authors":"Swapnil Bahl, Shrey Rungta, Shray Khullar, R. Kapur, A. Chandra, S. Talluto, Pramod Notiyath, Ajay Rajagopalan","doi":"10.1109/DFT.2014.6962079","DOIUrl":null,"url":null,"abstract":"STMicroelectronics has been using scan compression for many years. With the vast variety of designs and the size of the company it is important to deploy an easy to use solution that works for all the conditions. Today we support many different compression schemes DFTMAX, DFTMAX Xtol, Serializer. Each of these solutions is strong in a segment of the designs. DFTMAX Ultra has a technology that provides a single solution for all needs. In this paper we discuss the variety of design scenarios seen in ST from the point of scan compression. Results of DFTMAX Ultra are then presented to show that it is a viable unified solution.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Unifying scan compression\",\"authors\":\"Swapnil Bahl, Shrey Rungta, Shray Khullar, R. Kapur, A. Chandra, S. Talluto, Pramod Notiyath, Ajay Rajagopalan\",\"doi\":\"10.1109/DFT.2014.6962079\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"STMicroelectronics has been using scan compression for many years. With the vast variety of designs and the size of the company it is important to deploy an easy to use solution that works for all the conditions. Today we support many different compression schemes DFTMAX, DFTMAX Xtol, Serializer. Each of these solutions is strong in a segment of the designs. DFTMAX Ultra has a technology that provides a single solution for all needs. In this paper we discuss the variety of design scenarios seen in ST from the point of scan compression. Results of DFTMAX Ultra are then presented to show that it is a viable unified solution.\",\"PeriodicalId\":414665,\"journal\":{\"name\":\"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2014.6962079\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2014.6962079","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
STMicroelectronics has been using scan compression for many years. With the vast variety of designs and the size of the company it is important to deploy an easy to use solution that works for all the conditions. Today we support many different compression schemes DFTMAX, DFTMAX Xtol, Serializer. Each of these solutions is strong in a segment of the designs. DFTMAX Ultra has a technology that provides a single solution for all needs. In this paper we discuss the variety of design scenarios seen in ST from the point of scan compression. Results of DFTMAX Ultra are then presented to show that it is a viable unified solution.