Design and implementation of a self-healing processor on SRAM-based FPGAs

Abstract

This paper presents an approach to design and implement a soft-core processor on SRAM-based FPGAs able to autonomously deal with the occurrence of soft errors; state-of-the-art area-replication strategies are coupled with dynamic partial reconfiguration to detect faults and to consequently repair them. The reconfiguration process is performed by the processor itself using a minimum set of "critical" instructions and the logic responsible for their execution is hardened, to enable the self-healing property. The methodology is applied to the OpenRISC processor, evaluating costs and benefits.