J.M. Haemer, S. Sitaraman, D. Fork, F. Chong, S. Mok, D.L. Smith, F. Swiatowiec
{"title":"Flexible micro-spring interconnects for high performance probing","authors":"J.M. Haemer, S. Sitaraman, D. Fork, F. Chong, S. Mok, D.L. Smith, F. Swiatowiec","doi":"10.1109/ECTC.2000.853319","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853319","url":null,"abstract":"Advances in integrated circuit fabrication have given rise to a need for an innovative, inexpensive, yet reliable probing technology with ultra-fine pitch capability. Research teams at Georgia Tech, Xerox PARC, and Nanonexus, Inc. are developing flexible micro-spring structures that can far exceed the packaging and probing needs of the next-generation microelectronic devices. Highly compliant cantilevered springs have been fabricated at pitches as small as 6 /spl mu/m. These micro-springs are designed to accommodate topological variation in probing surfaces while flexing within the elastic regime. The micro-springs have demonstrated reliable electrical contact and mechanical ruggedness. Non-linear finite element models have been developed to understand the deformation of a micro-spring under mechanical loading. Through the models, the probing force versus displacement relation for a spring as well as the internal stress distribution have been determined. Design guidelines have been established to maximize probing force.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124878129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The effect of sliding wear on lubricated tin-lead contacts","authors":"N. Aukland, H. Hardee","doi":"10.1109/ECTC.2000.853321","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853321","url":null,"abstract":"Tin-based material systems are used extensively in connector interfaces, because tin based material systems are cost effective and have advantageous corrosion characteristics. One of the weaknesses of these material systems is poor wear characteristics. In general, connectors experience two different types of wear at their interfaces that will shorten their service life: sliding wear and fretting wear. This paper will concentrate on sliding wear, which occurs whenever a connector is mated and unmated. Data are presented for a series of sliding wear experiments, under 50 and 150 grams normal loads. The cyclic movement is 0.1 inch at 0.1 inch/sec. Wear-out of the connector interface has been determined by monitoring the dynamic coefficient of friction and by analysis of the wear track using an optical microscope. The benefit of using a special formulation of a CLT: X-10 lubricant at the interface to protect the tin/lead material system is demonstrated, through the use of a new first order sliding wear model.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124906675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low temperature fluxless bonding technique using In-Sn composite","authors":"S. Choe, W. So, C.C. Lee","doi":"10.1109/ECTC.2000.853130","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853130","url":null,"abstract":"Device packages usually need more than one soldering operation to complete. For photonic and fiber optics devices and packaging, indium solder has become ever more popular due to its ductility. Indium has a relatively low melting temperature of 156/spl deg/C. During subsequent bonding operations, another process with a bonding temperature lower than 156/spl deg/C is needed. Desirable bonding temperature should be lower than 156/spl deg/C but higher than the maximum temperature of the solder during device operation. In this paper, we report a new alternative to the conventional solder using In/Sn multilayer composite. This is a fluxless and oxidation-free soldering technique that has a bonding temperature of 140/spl deg/C. In fabrication, Cr/Sn/In/Au multilayer composite is deposited on bare silicon dice in one high vacuum cycle to prevent oxidation. Immediately upon deposition, Au and In react to form a stable AuIn2 protective outer layer against oxidation. Silicon substrates are deposited with thin Cr/Au layers. The silicon die and substrate are bonded in hydrogen environment at 140/spl deg/C. Scanning acoustic microscopy (SAM) analysis is used to evaluate the joint quality. This bonding technique consistently achieves uniform and void-free joints. SEM and EDX analyses also are performed on the joint cross sections. The SEM image shows uniform joint thickness of 5 /spl mu/m and joint microstructure. SEM and EDX results indicate the joint is consisted of In-Sn alloy with embedded AuIn2 grains. The re-melting temperature of several joints is measured. It ranges from 125/spl deg/C to 150/spl deg/C. This shows that the joint composition is not exactly eutectic that has a melting temperature of 118/spl deg/C, but rather is Sn-rich. This interesting result offers a very important advantage in that it increases the temperature that the device package can handle. The fluxless feature of this technology is valuable for bonding and assembling many emerging photonic devices that simply cannot tolerate flux.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122865011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Hauffe, U. Siebel, K. Petermann, R. Moosburger, J. Kropp, F. Arndt
{"title":"Methods for passive fiber chip coupling of integrated optical devices","authors":"R. Hauffe, U. Siebel, K. Petermann, R. Moosburger, J. Kropp, F. Arndt","doi":"10.1109/ECTC.2000.853156","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853156","url":null,"abstract":"A useful technique for high precision passive coupling of single mode optical fibres to integrated optical devices is crucial for cost effective packaging especially in multiport devices like switches and other WDM components. These devices were fabricated on two different material bases, SOI and polymers. In both cases the waveguides are based on the oversized rib waveguide concept and utilize silicon as a substrate. Two possible fabrication processes for this passive fiber chip coupling IN or ON silicon are presented and compared. The first approach involves a technology similar to flip chip fabrication using a sub- and superstrate, that allows a separate processing of V-grooves for fiber alignment and the integrated optical devices. The self aligned mounting of the chip is achieved by a V-shaped rib-groove combination created by wet chemical etching, where the rib is the exact negative of the groove so that the flip chip is put on precisely defined crystal planes rather than on sensitive edges. The second approach utilizes the same chip for waveguides and fiber alignment structures which makes it possible to define both in the same lithographic step and thereby eliminating any vertical displacement. Processing difficulties arise primarily from completely different processing requirements of fiber aligning V-grooves and integrated waveguides. The need to define patterns of the size of only several /spl mu/m in the proximity to deep grooves makes the use of an electrophoretic photoresist necessary. Both processes allow for fiber chip alignment precisions in the sub-/spl mu/m range which was also experimentally verified with coupling losses as low as 0.7 dB per end-face. The fabrication processes along with experimental and theoretical results are presented.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131250882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fine pitch probing and wirebonding and reliability of aluminum capped copper bond pads","authors":"T. Tran, L. Yong, B. Williams, S. Chen, A. Chen","doi":"10.1109/ECTC.2000.853444","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853444","url":null,"abstract":"The requirement for improved electrical performance and reduced silicon area has driven Copper to replace Aluminum interconnection as silicon technology is scaled beyond 0.25 /spl mu/m. The front-end change, in turn, pushes wirebond pad pitch from above 100 /spl mu/m to 80 /spl mu/m-66 /spl mu/m range. This creates challenges for back-end to probe and wire bond at fine pitch geometry onto a readily oxidized Copper surface. After several re-metallization structures and types of metallurgy were evaluated, capping Copper bond pads with Aluminum was selected as the primary approach for probing and wirebonding Copper devices. Aluminum re-metallization structure offers many advantages that help leverage existing tooling and knowledge in fab, probing and wire bonding processes. This paper will describe probe and wirebond experiments used to select the proper adhesion and diffusion barrier between Copper and Aluminum, and Aluminum thickness that can withstand the mechanical stress during probing and wire bonding. Probe mark depth and the impact of probe marks to the underlying barrier and Copper pad were examined. Ball shear, wire rip and corresponding failure modes, intermetallic coverage and cratering analysis were evaluated at various readpoints of thermal aging study to evaluate the integrity of the re-metallization structure as well as the quality of ball bonds onto the new structure. Contact resistance measurement and reliability assessment were also performed. One re-metallization structure was recommended for Copper High Performance wire bonded devices.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131590379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mixed signal system design course development","authors":"H. Tenhunen","doi":"10.1109/ECTC.2000.853295","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853295","url":null,"abstract":"This paper covers the current curriculum approach to system level integration at Royal Institute of Technology. Our approach is system driven with systematic emphasis of interconnect centric issues in all design phases and abstraction levels. The overall curriculum provides physical, design process (methodology), and functional view of the complex electronic system. Our focus in this paper is to describe the motivation and the specific content of the physical or implementation view. The key feature is enhancing student's capability to build systematically multiple abstractions of the technology and physical issues and constraints for efficient conceptual co-design of ICs and packages and interconnect substrates and for design space exploration. A major effort in Mixed Signal System Design course is devoted for understanding the electrical design and technology issues and interactions of chip and package for complex gigascale integrated systems. The objectives of this new course package is to give Swedish electronics industries world class engineering resources in strategic areas for system integration to final HW/SW products. The overall program is also available as International M.Sc. Program starting fall term 2000.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115173460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated fiber attachment for 980 nm pump modules","authors":"P. Mueller, B. Valk","doi":"10.1109/ECTC.2000.853107","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853107","url":null,"abstract":"Automation is the keyword for further fast progress at reasonable prices in telecommunication device production. Up to now most assembly procedures are still performed manually because of the very different nature of the components such as fibers, laser diodes, thermoelectric coolers, lenses etc., their high price and low product volumes. For 980 nm pump laser modules, the most crucial and time-consuming assembly-step is the fiber to laser diode attachment. Here, mostly a multi-part structure is used for longtime stability fixing of a lensed fiber in respect-to a mounted laser diode. This structure is designed for fixing by laser welding and allows. A consecutive fine adjustment by mechanical plastic deformation. At JDS Uniphase in Zurich, new design concepts with respect to the automation point of view were studied and implemented. As a result, all the necessary parts and functions could be included in one structure design, the so-called 'all-in-one' clip (pat.pending). This clip allows simpler part handling, a more stable and automated welding/fine adjustment and smaller cycle times with the same longtime stability as test results for coupling efficiencies, fixing losses, vibration and temperature cycling tests show.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121257576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High accuracy machine automated assembly for opto electronics","authors":"G. Lecarpentier, J. Mottet, J. Dumas, K. Cooper","doi":"10.1109/ECTC.2000.853099","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853099","url":null,"abstract":"One of the major alignment challenges faced by assembly engineers today is the accurate assembly of high-end optoelectronic modules. Silicon optical platform applications, where a laser diode is aligned to a single mode fiber or an optical waveguide, require post-bonding alignments better than 1 micron for optimum device performance. Flip Chip technology has proven its ability to cope with such stringent alignment requirements. Several bonding methods have been investigated, ranging from active alignment of a powered device to various forms of passive self-aligned soldering methods employing one or more mechanical stops. Though these methods have demonstrated some good results, the active alignment method incurs substantial cost of assembly time, while some self-aligning methods carry the disadvantage of requiring additional process steps during chip and substrate fabrication, as well as generating more sporadic alignment results under typical manufacturing variations. A passive alignment approach is proposed, where the mechanical alignment, placement and joining burdens are bourne by a flip chip bonder. Differing substantially from pick and place machines available on the market today, this new flip chip bonder has been specifically aimed at the special requirements of the optoelectronic module market, and is capable of performing in-situ gold-tin eutectic bonding to 1 micron accuracy. The design and application of this bonder to this assembly process is reviewed, with special notice given to optical, thermal and environmental requirements.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132569496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Karstensen, F. Auracher, N. Ebel, J. Fiedler, V. Plickert, L. Melchior, L. Leininger, M. Bittner, M. Festag, M. Wicke, S. Meyer, R. Miller, G. Kuhn, H. Althaus, A. Ebberg
{"title":"Module packaging for high-speed serial and parallel transmission","authors":"H. Karstensen, F. Auracher, N. Ebel, J. Fiedler, V. Plickert, L. Melchior, L. Leininger, M. Bittner, M. Festag, M. Wicke, S. Meyer, R. Miller, G. Kuhn, H. Althaus, A. Ebberg","doi":"10.1109/ECTC.2000.853200","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853200","url":null,"abstract":"This paper discusses module packaging aspects with regard to high-speed data transmission for both single channel serial and multi channel parallel transmission. The increasing demand for bandwidth and data throughput of opto-electronic modules leads to continuously changing design rules for these modules. These rules are now completely different compared to those of the time of 100 Mbit/s transmission with light emitting diodes. More specifically, one of the key parameters or figure of merit in today's system design is the data throughput per board edge of the printed circuit boards of the corresponding electronic systems, e.g. switches, routers, clustered computers etc. This has a twofold effect on the module design and the module packaging: firstly, the transmission speed of the module has to be continuously increased, and secondly, the size of the module has to be shrunk. The first requirement leads directly to challenges with electromagnetic interference due to the bandwidth increase, the second to challenges in connector technology, precision of fabrication techniques, and, most severe, to challenges in heat dissipation as now at least the same number of watts of power has to be dissipated in a smaller volume. Both requirements together, of course, multiply the requirements on module packaging. In this paper comparisons of pin through hole, lead frame and ball grid array packages are given. Examples like a 2.5 Gbit/s Small Form Factor serial transceiver, a 2.5 Gbit/s OC48 transceiver with parallel electrical connections, first results of a 10 Gbit/s transceiver with opto-electronic components in a TO package, and 12/spl times/2.5 GBd parallel optical transmitter and receiver (Paroli) are presented. Requirements given by standard assembly techniques like pick-and-place ability and reflow solderability are discussed.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133281782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Chun, M. Swaminathan, L. D. Smith, J. Srinivasan, Zhang Jin, M. Iyer
{"title":"Physics based modeling of simultaneous switching noise in high speed systems","authors":"S. Chun, M. Swaminathan, L. D. Smith, J. Srinivasan, Zhang Jin, M. Iyer","doi":"10.1109/ECTC.2000.853245","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853245","url":null,"abstract":"Simultaneous Switching Noise (SSN) has become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex due to the thousands of interconnects that need to be analyzed. This is because a system level modeling approach is necessary that combines the chip, package and board level interactions. This paper presents an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition. This approximation is valid at frequencies where skin effect is dominant. Simulation results are compared with the measurements on a Test Vehicle, verifying the validity of the method.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133023120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}