Module packaging for high-speed serial and parallel transmission

H. Karstensen, F. Auracher, N. Ebel, J. Fiedler, V. Plickert, L. Melchior, L. Leininger, M. Bittner, M. Festag, M. Wicke, S. Meyer, R. Miller, G. Kuhn, H. Althaus, A. Ebberg
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引用次数: 9

Abstract

This paper discusses module packaging aspects with regard to high-speed data transmission for both single channel serial and multi channel parallel transmission. The increasing demand for bandwidth and data throughput of opto-electronic modules leads to continuously changing design rules for these modules. These rules are now completely different compared to those of the time of 100 Mbit/s transmission with light emitting diodes. More specifically, one of the key parameters or figure of merit in today's system design is the data throughput per board edge of the printed circuit boards of the corresponding electronic systems, e.g. switches, routers, clustered computers etc. This has a twofold effect on the module design and the module packaging: firstly, the transmission speed of the module has to be continuously increased, and secondly, the size of the module has to be shrunk. The first requirement leads directly to challenges with electromagnetic interference due to the bandwidth increase, the second to challenges in connector technology, precision of fabrication techniques, and, most severe, to challenges in heat dissipation as now at least the same number of watts of power has to be dissipated in a smaller volume. Both requirements together, of course, multiply the requirements on module packaging. In this paper comparisons of pin through hole, lead frame and ball grid array packages are given. Examples like a 2.5 Gbit/s Small Form Factor serial transceiver, a 2.5 Gbit/s OC48 transceiver with parallel electrical connections, first results of a 10 Gbit/s transceiver with opto-electronic components in a TO package, and 12/spl times/2.5 GBd parallel optical transmitter and receiver (Paroli) are presented. Requirements given by standard assembly techniques like pick-and-place ability and reflow solderability are discussed.
模块封装适用于高速串行和并行传输
本文讨论了单通道串行和多通道并行高速数据传输的模块封装问题。随着对光电模块带宽和数据吞吐量需求的不断增长,光电模块的设计规则也在不断变化。这些规则现在与使用发光二极管传输100 Mbit/s的时间完全不同。更具体地说,在当今的系统设计中,一个关键参数或指标是相应电子系统(如交换机、路由器、集群计算机等)的印刷电路板的每板边缘的数据吞吐量。这对模块设计和模块封装有双重影响:一是要不断提高模块的传输速度,二是要缩小模块的尺寸。由于带宽的增加,第一个要求直接导致了电磁干扰的挑战,第二个要求是连接器技术的挑战,制造技术的精度,最严重的是,散热的挑战,因为现在至少相同数量的功率必须在更小的体积中消散。当然,这两种需求加在一起会增加对模块封装的需求。本文对引脚通孔封装、引线框架封装和球栅阵列封装进行了比较。举例来说,如2.5 Gbit/s小尺寸串行收发器,2.5 Gbit/s OC48收发器与并联电连接,10 Gbit/s光收发器与光电元件在一个TO封装,12/spl倍/2.5 GBd并行光收发器(Paroli)的初步结果。讨论了标准装配技术的要求,如拾放能力和回流焊性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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