2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)最新文献

{"title":"A novel low-cost small-form-factor transceiver module","authors":"W. Hogan, D.P. Gaio, M.S. Cohen, J. Trewhella","doi":"10.1109/ECTC.2000.853239","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853239","url":null,"abstract":"A key trend in the optoelectronic data-communication industry is the move towards lower cost and smaller transceivers. This trend has driven transceiver modules to the Small-Form-Factor (SFF) dimensions, requiring SFF optical connectors, resulting in a cost lower than their larger predecessors (for example GBICs or 1/spl times/9 transceivers based on the larger duplex SC optical connector). The design and implementation of a low-cost SFF fiber optic transceiver based on the SFF LC fiber optic connector is discussed. Since most of the transceiver cost is associated with the optical subassemblies (OSAs), low cost, yet smaller OSAs are required. In addition, the entire transceiver assembly has been optimized for cost reduction by using direct-chip-attach electronics, and surface-mount components all mounted on a single card that snaps into a plastic-molded retainer. These SFF LC transceivers are well suited for Gigabit Ethernet, Fibre Channel, and 1394b applications, along with other applications requiring low cost data transfer at data rates of 1.25 Gb/s to 2.125 Gb/s, or higher.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116912192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of a 2D connector for coupling a 4/spl times/8 array of small diameter plastic optical fiber (117/125 /spl mu/m) to RCLED or VCSEL arrays","authors":"T. Coosemaus, A. Van Hove, K. Naessens, L. Vanwassenhove, P. van Daele, R. Baets","doi":"10.1109/ECTC.2000.853332","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853332","url":null,"abstract":"Currently, the data communication and interconnect world is marked by an ever increasing demand of data density, compactness and efficiency. In the past, serial links were gradually replaced by 1D parallel data communication through fiber arrays. A possible further route towards even higher density and aggregate capacity is to move towards 2D parallel fiber arrays. In this paper, we report on the fabrication of a prototype 2D-connector that in a later stage can be replicated using standard molding techniques. In our application, in view of cost and flexibility reasons, polymer optical fiber (117 /spl mu/m core/125 /spl mu/m cladding diameter, NA=0.5) is used as medium for short distance 2D links for inter-chip interconnections.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127469062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder bars-a novel flip chip application for high power devices","authors":"P. Elenius, H. Yang, R. Benson","doi":"10.1109/ECTC.2000.853234","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853234","url":null,"abstract":"The compatibility of conventional flip chip technology for high power/high current applications can present functional and reliability issues during the device operating life. Typical flip chip solder bumps can experience early failures due to electromigration when exposed to a high current density at a given junction temperature. As a viable alternative, the solder bar approach was developed to increase the cross-sectional area of the solder joint, there by reducing current density and improving device operating life.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"43 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123437167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LOC tape design for protecting integrated circuit pattern from damage due to a dicing saw blade","authors":"Seong-Min Lee","doi":"10.1109/ECTC.2000.853426","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853426","url":null,"abstract":"In general, the scribing position of a dicing saw blade is close to the IC (integrated circuit) device because the mounting density of the separated IC device (i.e. productibility or yield) increases by the reduced dimension of the scribe regions. So, the IC patterns are not free from mechanical damage due to the dicing saw blade. In the present study, in order to protect the IC patterns from the impact due to the dicing saw blade, the pattern layers on the scribe regions of a semiconductor wafer are selectively removed and so, the bare silicon surface is exposed therein. The scribe regions (where the layers are absent) are then replaced by polyimide prior to the wafer dicing process. Since the polyimide film has a considerably larger adhesion strength with the silicon surface, compared with other pattern layers or plastic-encapsulants, it effectively absorbs the force of the impact of the saw blade.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"442 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123586121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of active and passive fiber alignment techniques for multimode laser pigtailing","authors":"P. Karioja, J. Ollila, Veli-Pekka Putila, K. Keranen, J. Hakkila, H. Kopola","doi":"10.1109/ECTC.2000.853157","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853157","url":null,"abstract":"When packaging multimode lasers into low-cost modules, passive fiber alignment would be extremely advantageous especially if the fiber alignment structures could be manufactured using the injection-molding technique. Injection molding as large-volume manufacturing technique allows for the reduction of the unit price of molded parts provided that the number of parts molded by using a single molding tool is large. In this paper, we compare active and passive fiber alignment techniques. The construction and packaging procedures of two modules packaged using active and passive alignment techniques are shown. Using a sleeve construction, a multimode laser with a 230 /spl mu/m/spl times/2 /spl mu/m emitting area was actively pigtailed with a 100/140-/spl mu/m multimode fiber. In the other example, a multimode laser with a 300 /spl mu/m/spl times//spl sim/1 /spl mu/m emitting area was passively pigtailed with a 200/230-/spl mu/m multimode fiber by the use of an alignment structure, which was precision-machined using LIGA technique. The study shows the applicability of the passive alignment technique for low-cost fiber pigtailing.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125289168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Progress in electronics packaging virtual laboratory development","authors":"P. Gordon, P. Bojta, L. Hertel, I. Kallai, I. Lepsenyi, L. Varnai, Z. Illyefalvi-Fitez","doi":"10.1109/ECTC.2000.853342","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853342","url":null,"abstract":"The development of information technology has opened new perspectives in electronics packaging education to prepare engineers for the needs of the 21/sup st/ century. The Department of Electronics Technology has been working on the improvement of the education in this respect for many years. It has obtained an IEEE/NSF grant in 1999 to create the Virtual Laboratory, a solution of the educational support with the newest and high-quality Web-technology. This paper gives a summary of the results of the one-year long practical development.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114960179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flip chip interconnect systems using wire stud bumps and lead free solder","authors":"S. Zama, D. Baldwin, T. Hikami, H. Murata","doi":"10.1109/ECTC.2000.853310","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853310","url":null,"abstract":"This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire bumping. Cu wire studs were bumped by controlling the ramp of ultrasonic power to eliminate the occurrence of under-pad chip cracks which tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu alloy was used to interconnect the wire studs and printed circuit board. A comparison is made with conventional eutectic 63Sn37Pb alloy and 60In40Pb alloy. A more stable solder connection was created when Cu wire stud bumps were used, compared with Au wire stud bumps. The improved stability is due to reduced intermetallic compound formation with the solder alloy. Test vehicles were assembled with two different Direct Chip Attachment (DCA) processes. When a conventional flip chip assembly and reflow was used, the lead free test vehicles exhibited process failure. On the other hand, when solder reflow and underfill cure were performed at the same time by using a high accuracy flip chip bonder, the reliability of lead free test vehicles in thermal shock improved.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115195932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Materials challenges for wafer-level flip chip packaging","authors":"B. Ma, Q. Tong, E. Zhan, Sunhee Hong, A. Savoca","doi":"10.1109/ECTC.2000.853142","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853142","url":null,"abstract":"Flip chip as the smallest packaging design has been used in more and more electronic applications. Flip chip underfill is an essential component for the reliability of the package. Currently, the dispensing process is done at each individual chip level after interconnects have been made. The device then has to go through a separate curing process to harden the underfill material. This process is cumbersome and is one of the cost drivers of flip chip application. In wafer level flip chip packaging, the dispensing is made over the whole wafer in one step. After dicing, the reflow and the curing of underfill will be accomplished also in one step. The saving on process cost will be significant. The new process brings new challenges to underfill development. In addition to performing the reinforcement role as an underfill, these new materials have to act as a fluxing agent for solder reflow. They also have to have good room temperature stability after being dispensed onto wafer, handled at ambient environment, and before being cured in the reflow oven. The author will discuss parameters that determine the material performance at each processing step as well as the material development effort undergoing in a wafer-level underfill development program, which is sponsored by the Advanced Technology Program (ATP).","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129419147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Vibration fatigue of /spl mu/BGA solder joint","authors":"P. Tu, Y. Chan, C. Tang, J. Lai","doi":"10.1109/ECTC.2000.853388","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853388","url":null,"abstract":"This paper studies the vibration fatigue failure of /spl mu/BGA solder-joints reflowed with different temperature profiles, and ageing at 120/spl deg/C for 1, 4, 9, 16, 25, 36 days. The effect of the thickness of the Ni/sub 3/Sn/sub 4/ and Cu-Sn intermetallic compound (IMC) on the fatigue lifetime is also reported. During the vibration fatigue test, in order to identify the failure of /spl mu/BGA solder joint, electrical interruption was monitored continuously through the daisy-chain network. Our results show that the fatigue lifetime of the solder joint firstly increases and then decreases with increasing heating factor (Q/sub n/), which is defined as the integral of the measured temperature over the dwell time above liquidus (183/spl deg/C) in the reflow profile. The greatest lifetime occurs when Q/sub n/ is near 500 s/spl deg/C. Moreover, the lifetime of the solder joint decreases linearly with the increasing fourth root of the ageing time. The SEM/EDX inspection shows that only Ni/sub 3/Sn/sub 4/ IMC and Cu/sub 6/Sn/sub 5//Cu/sub 3/Sn IMCs are formed between the solder and the nickel-plated PCB pad, and the solder/component-metallization interface respectively. For non-aged samples reflowed with different profiles, the fatigue crack generally initiates at valleys in the rough surface of the interface of the Ni/sub 3/Sn/sub 4/ IMC with the bulk solder. Then it propagates mostly near the Ni/solder, and occasionally in the IMC layer or along the Ni/solder interface. For aged samples, the fatigue crack mostly initiates and propagates in the Cu/sub 6/Sn/sub 5/-phase/bulksolder interface or the Cu/sub 3/Sn/Cu/sub 6/Sn/sub 5/ interface on component-metallization. Evidently, the intermetallic compounds contribute mainly to the fatigue failure of /spl mu/BGA solder joints. The thicker the IMC layer, the shorter the fatigue lifetime of solder joint. The initial formation of the IMCs at the interface during soldering ensures a good metallurgical bond between the solder and the substrate. However, a thick IMC layer influences the solder joint strength, which results in mechanical failure due to volume shrinkage during the transformation from solid phase to the intermetallic compound.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129565074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of Chip-on-Dot flip chip technique utilizing Gold Dot/sup TM/ flexible circuitry","authors":"Z. Wang, Y. M. Tan, C. Schreiber, C. Tsui, Z. Shi, J. Wei","doi":"10.1109/ECTC.2000.853406","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853406","url":null,"abstract":"A novel flip chip assembly technique, called Chip-on-Dot, has been developed for assembling chips which does not mandate either under-bump metallization (UBM) treatment to the aluminum input/output pads or die bumping. Instead, the die are flipped upon flexible Gold Dot/sup TM/ substrates possessing raised contact features integral to the circuitry. The copper conductors possess small and exactingly shaped raised contact bumps (Gold Dots). When the Al die pads are aligned and pressed upon the mating dots of the substrate in conjunction with temperature, diffusion between aluminum and gold establishes an inter-metallic bond layer at the contact interfaces. Electrical connection is thus established. A non-electrically conductive adhesive, which is dispensed prior to bonding and simultaneously snap cured during the bonding process enhances the mechanical integrity of these interconnections. Finite element contact analysis was conducted to study the pressure distribution in the contact area of a dot. By simulating the Chip-on-Dot assembly process, the optimal dot geometry was designed which provided a uniform contact pressure across the contact area. This additionally promoted diffusion bonding across the whole contact area and produced little damage to the Al pads. Using the PCMCIA card format, an electrically functional prototype was constructed and populated with 12 die using the Chip-on-Dot technique. Subsequently, the test vehicle was subjected to accelerated environmental testing. The following test results show that this assembly process is robust for commercial packaging applications.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129732918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}