Materials challenges for wafer-level flip chip packaging

Abstract

Flip chip as the smallest packaging design has been used in more and more electronic applications. Flip chip underfill is an essential component for the reliability of the package. Currently, the dispensing process is done at each individual chip level after interconnects have been made. The device then has to go through a separate curing process to harden the underfill material. This process is cumbersome and is one of the cost drivers of flip chip application. In wafer level flip chip packaging, the dispensing is made over the whole wafer in one step. After dicing, the reflow and the curing of underfill will be accomplished also in one step. The saving on process cost will be significant. The new process brings new challenges to underfill development. In addition to performing the reinforcement role as an underfill, these new materials have to act as a fluxing agent for solder reflow. They also have to have good room temperature stability after being dispensed onto wafer, handled at ambient environment, and before being cured in the reflow oven. The author will discuss parameters that determine the material performance at each processing step as well as the material development effort undergoing in a wafer-level underfill development program, which is sponsored by the Advanced Technology Program (ATP).