2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)最新文献

{"title":"An analysis of interface delamination in flip-chip packages","authors":"L. Mercado, V. Sarihan, T. Hauck","doi":"10.1109/ECTC.2000.853350","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853350","url":null,"abstract":"Interface delamination is an important failure mode for flip-chip PBGA (plastic ball grid array) packages. It plays a significant role on package performance and reliability. In this paper, a fracture mechanics approach is utilized to evaluate the impact of interface delamination on package reliability. Interface cracks are mixed mode cracks with both mode I (opening mode) and mode II (shear mode) components. To characterize the interfaces in electronic packages, it is essential to define the interfacial toughness as a function of different mode mixity, or loading phase angle. In this paper, interface fracture mechanics is incorporated into finite element analysis to determine the critical interface fracture parameters. The proposed methodology is validated against analytical solutions. A Flip-Chip PBGA package with underfill delamination is studied. The effect of temperature, initial delamination length, package geometry and materials on the fracture parameters is evaluated.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"14 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132120350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved bonding pad design for fluxless flip chip bonding process and low fracture strength substrates","authors":"R. Bonda, Y. Guo, J. Stafford, G. Swan","doi":"10.1109/ECTC.2000.853449","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853449","url":null,"abstract":"A fluxless flip-chip bonding process and a metallized glass substrate have been used for the development of an optical display module. Two major problems were encountered with this design and the bonding process that affected both the assembly yield and reliability of the modules. One was, in the absence of flux, holding the chip in place on the bonding pads until the solder reflow had been difficult. This resulted non-wets and low assembly yield. The other problem was, fracture of the glass around and underneath the bonding pads during flip chip bonding and subsequent reliability tests. Incorporating \"donut hole\" structure in the bonding pads provided excellent tacking, as the solder deformed into these donut hole structures, and held the chip in place until the solder reflow. This dramatically improved the assembly yield. Covering the bonding pad edges with passivation, which modified the stress state around the bonding pads, eliminated the latter problem (fracture of glass).","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133798703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent experiences on developing multimedia educational modules","authors":"B.C. Kim","doi":"10.1109/ECTC.2000.853344","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853344","url":null,"abstract":"This paper describes recent experiences on developing multimedia educational modules for electronics packaging at Michigan State University (MSU). For the last two years, Michigan State University has been involved in teaching the graduate level packaging course. The course is designed to cover multi-disciplinary subjects in electronics packaging. During the course development, some multimedia modules were developed using Synch-O-Matic software tool. These lecture modules can be downloaded from the MSU Web site for individual learning and review. We have received some start-up funding from the IEEE CPMT Society and the National Science Foundation to develop more modules that are critical in electronics packaging education. These modules will be shared with other Universities and industry via the Internet Web. Some of the specific modules that we plan to develop are in the areas of Interconnect Modeling, Embedded Passives, Package Electrical Testing, and Package Layout. We plan to have a class where students can participate and learn packaging education using the Internet. The Web based lectures will contain sound, video and synchronized lecture notes on a PC. The lectures will consist of Real-Video Player with synchronized PowerPoint presentations. These lectures will be viewable over a 28.8 K modem or faster connection.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124020419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An all purpose dispersive multiconductor interconnect model compatible with PRIMA","authors":"S. Pasha, A. Cangellaris, J. Prince","doi":"10.1109/ECTC.2000.853206","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853206","url":null,"abstract":"This paper describes a new, transmission line-based discrete model for interconnects with per-unit-length, frequency-dependent resistance and inductance. The proposed model is developed in such a manner that the resulting discrete form of Telegrapher's equations constitutes a passive system, and is compatible with passive, reduced-order macromodeling algorithms. The validity of the proposed model is demonstrated through numerical examples.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127926555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Epoxy adhesives for optical element attachment in planar passive optical components","authors":"J.G. Liu, B. M. Andersen, E. Bergmann, S. Fairchild","doi":"10.1109/ECTC.2000.853286","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853286","url":null,"abstract":"Optical elements are bonded to the planar housing with adhesive materials for applications in a non-hermetic package of integrated passive optical devices. Eight epoxy adhesives have been evaluated in order to select the most suitable adhesive for use in a high-speed, automated assembly production facility. Tests were performed to examine the angular alignment accuracy and to determine the long-term adhesion and stability of the epoxy bonded components. Our results show that a thixotropic epoxy having high green strength, minimal shrinkage on cure, low outgassing and high resistance to humidity environment is suitable for bonding optical elements for the application.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121215130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single level integrated packaging modules for high performance electronic systems","authors":"Lirong Zheng, H. Tenhunen","doi":"10.1109/ECTC.2000.853404","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853404","url":null,"abstract":"In this paper, we introduce a novel packaging scenario that aims to integrate or eliminate the existing multilevel packaging hierarchies towards single level integration. The new approach is actually an extension of VLSI technology where standard IC processes were pursued in the whole fabrication sequence. Test samples were made successfully. The module and interconnect structures, integration process, and electrical performance were studied theoretically and experimentally. Properties of signal propagation and coupling from chip to chip were simulated and measured in frequency domain as well as in time domain. It shows that off-chip communication with several Gb/s data rate is possible in such modules.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Squeegee bump technology","authors":"Jong-Kai Lin, T. Fang, R. Bajaj","doi":"10.1109/ECTC.2000.853115","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853115","url":null,"abstract":"An innovative solder bumping technology, termed squeegee bumping, has been developed et Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to stencil printing and therefore exhibits better versatility of solder materials selection than the electroplating process. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118/spl plusmn/3.5 /spl mu/m, and a maximum-to-minimum bump height range of 17 /spl mu/m over a 150 mm-diameter wafer have been produced repeatedly on test wafers with 210 /spl mu/m peripheral pitch. A 109.6/spl plusmn/1.3 /spl mu/m bump height on orthogonal array with 250 /spl mu/m pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10/spl times/ reflows and 1008 hours of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55/spl deg/C to +125/spl deg/C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 hours of autoclave stress at 121/spl deg/C, 100%RH, 15 psig test condition.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1688 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129377233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A study of solder paste flow inside a sealed printing head","authors":"D. He, Nduka Nnamdi (Ndy) Ekere","doi":"10.1109/ECTC.2000.853136","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853136","url":null,"abstract":"In the assembly of Printed Circuit Boards (PCBs) using Surface Mount Technology (SMT), solder paste is deposited on the bond pads of the PCBs using stencil/screen printing technique. The last few years have seen the development and introduction of new printing mechanism to meet the miniaturisation challenge of electronic products. The most notable is the development of new printing heads such as the ProFlow and the Rheometric Pumping Head. Unlike the traditional squeegee blade, in these new printing devices the solder paste is contained in a sealed pressurised chamber, and is released during the printing stroke via an opening as the printing head passes over the stencil apertures. The flow profile of the solder paste inside such a chamber plays a key role in determining the volume of solder paste deposited onto the PCB pads. In this paper we investigate the paste flow inside such a chamber and its influence on the aperture filling. Our results show that the paste does not vertically fill the apertures, but has a horizontal velocity component in the printing direction. This horizontal velocity component will lead to insufficient filling of paste at the rear corner of the aperture. To counteract the influence of this undesirable velocity component, we propose to introduce a horizontal shaft perpendicular to the printing direction inside the chamber. During a printing stroke this shaft rotates inside the chamber in the printing direction and drives the paste near the bottom slot to flow against the printing direction. We present an analysis of the paste flow inside such a device and the nature of the aperture filling process. The main parameters that influence the paste flow are the diameter, the rotational speed and the position of the shaft. The key to obtaining sufficient and consistent paste deposits is to minimise the horizontal velocity component of the paste to ensure the paste fills into the aperture vertically, and to maximise the vertical velocity component of the paste to shorten the aperture filling time. The introduction of such a shaft is also expected to significantly reduce the pressure loading on the paste at the top of the chamber.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128408507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low cost wafer-level CSP: a novel redistribution methodology","authors":"G. Rinne, J. Wallin, J. D. Mis","doi":"10.1109/ECTC.2000.853125","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853125","url":null,"abstract":"A chip scale package using wafer scale processing was developed for a line of low cost, small form factor integrated circuits. The package uses polymeric repassivation and electrodeposited solder bumps connected by a unique conductor patterning method. As an alternative to the aluminum redistribution approach for converting wirebond designs to CSP, a low cost method was developed. Called single-mask redistribution (SMR), this process creates the solder bump and the redistribution line in a single patterning step. Solder is plated to an equal height on both the line and the bump pad and, during reflow, hydrostatic pressure causes the excess solder on the line to flow to the bump. The finished package resembles a common chip resistor. Reliability testing was used to optimize the bump design and the assembly methodologies. Field performance of more than 30 million packages has validated the test results.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117005947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An overview of MCM/KGD development activities in Japan","authors":"T. Sudo","doi":"10.1109/ECTC.2000.853253","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853253","url":null,"abstract":"The MCM/KGD study group in EIAJ (Electronic Industries Association of Japan) surveyed the activities on MCM related technologies and the future perspectives up to 2010. The high density packaging technology had been driven by supercomputers and mainframes for a long time. Recently, high performance microprocessors become available for consumer products such PDAs (personal digital assistants), Notebook PCs (personal computers), digital cameras and so on. Then, MCM is a key technology to make these consumer products smaller, lighter and thinner. Area array packages such as BGA (ball grid array), CSP (chip scale package) are key components to reduce the occupied area. Wafer-level CSP will be a new approach to supply KGD in a minimum assembly cost by handling in a wafer level instead of a die level. Build-up type printed circuit board is essential to mount both CSPs and flip-chipped dies with fine-pitch I/O terminals. Test methodology for burn-in and testing must be improved to provide low cost KGD (Known good die) in the future.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117256665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}