Squeegee bump technology

Abstract

An innovative solder bumping technology, termed squeegee bumping, has been developed et Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to stencil printing and therefore exhibits better versatility of solder materials selection than the electroplating process. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118/spl plusmn/3.5 /spl mu/m, and a maximum-to-minimum bump height range of 17 /spl mu/m over a 150 mm-diameter wafer have been produced repeatedly on test wafers with 210 /spl mu/m peripheral pitch. A 109.6/spl plusmn/1.3 /spl mu/m bump height on orthogonal array with 250 /spl mu/m pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10/spl times/ reflows and 1008 hours of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55/spl deg/C to +125/spl deg/C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 hours of autoclave stress at 121/spl deg/C, 100%RH, 15 psig test condition.