2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)最新文献_第5页

Bandwidth prediction for high-performance interconnections 高性能互连的带宽预测

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853160

A. Deutsch, G. Kopcsay, P. Coteus, C. Surovic, P. Dahlenz, D. Heckmann, D. Duan

引用次数: 7

High speed, high performance laser module 高速、高性能激光模块

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853197

A. Benzoni, M. Downie, B. Kasper, J. Paslaski, E. Peral, X. Wu, T. Schrans, M. Swass, C. Tsai, I. Ury

{"title":"High speed, high performance laser module","authors":"A. Benzoni, M. Downie, B. Kasper, J. Paslaski, E. Peral, X. Wu, T. Schrans, M. Swass, C. Tsai, I. Ury","doi":"10.1109/ECTC.2000.853197","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853197","url":null,"abstract":"We will present the performance data and discuss a few pertinent design details of a cooled directly modulated laser (DML) module that is targeted for use in several SONET OC-192 applications and capable of addressing 10G Ethernet requirements. The intent of the presentation is to demonstrate the performance potential of the module operating at 1310 nm wavelength for these applications. The four primary technical areas of focus are: (1) the ability to continuously operate in adverse environmental conditions, i.e. 85/spl deg/C case temperature, (2) demonstrate transmission up to 80 km is achievable via use of, (3) a high efficiency optical coupling design, and (4) ease of RF interface due to low RF return loss and high bandwidth. These all assume that the laser's intrinsic design is properly specified and well matched to the package design. The regime of engineering design is approaching the practical limits and diminishing returns in terms of RF and optical coupling efficiencies. This suggests that further substantial improvements require a change in the underlying technology.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125549245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging 晶圆厂集成封装(FIP):高可靠性晶圆级芯片尺寸封装的新概念

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853121

M. Topper, J. Auersperg, V. Glaw, K. Kaskoun, E. Prack, B. Keser, P. Coskina, D. Jáger, D. Fetter, O. Ehrmann, K. Samulewicz, C. Meinherz, S. Fehlberg, C. Karduck, H. Reichl

{"title":"Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging","authors":"M. Topper, J. Auersperg, V. Glaw, K. Kaskoun, E. Prack, B. Keser, P. Coskina, D. Jáger, D. Fetter, O. Ehrmann, K. Samulewicz, C. Meinherz, S. Fehlberg, C. Karduck, H. Reichl","doi":"10.1109/ECTC.2000.853121","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853121","url":null,"abstract":"Wafer Level Packaging has the highest potential for future single chip packages. The package is completed directly on the wafer then singulated by dicing for the assembly in a flip chip fashion. All packaging and testing operations of simulated dice will be replaced by whole wafer fabrication and wafer level testing. The result is a technology which leads the way to Fab Integrated Packaging (FIP). An evaluation of the reliability of a new Wafer-Level Chip Scale Package (WL-CSP) was done in the FIP program, a joint development program between Fraunhofer IZM and Motorola. As a CSP the FIP-CSP eliminates underfill operation during flip-chip bonding using high through-put SMT assembly lines. The technological structure of this FIP-CSP is a pad redistributed die with a solder ball array. A stress compensation layer (SCL) embeds the solder balls before second solder balls are stencil printed or placed on top of embedded balls. The reliability of this wafer-level CSP presented here was simulated and evaluated by test samples. The test chip was a 1 cm/spl times/1 cm square chip which was redistributed to an 14/spl times/14 ball array with a pitch of 0.5 mm. JEDEC Level 3, 1000 cycles AATC (-55/spl deg/C/+125/spl deg/C) and 48 h Autoclave on component level were passed. On board level 1000 hours humidity storage at 85/spl deg/C (85/85 test) and 1000 cycles -55/+125/spl deg/C were passed.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123237220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Low profile package technology for IrDA compliant transceivers 符合IrDA标准的收发器的低规格封装技术

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853410

V. Nitsche

引用次数: 0

Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard small outline packages 与标准的小轮廓封装相比，使用凹凸芯片载波封装的rfic的电气性能有所提高

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853192

T. Horng, S. Wu, J. Li, C. Chiu, C. Hung

引用次数: 8

Under bump metallizations for lead free solders 无铅焊料的凹凸金属化

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853309

T. Korhonen, P. Su, S. Hong, M. A. Korhonen, C.Y. Li

{"title":"Under bump metallizations for lead free solders","authors":"T. Korhonen, P. Su, S. Hong, M. A. Korhonen, C.Y. Li","doi":"10.1109/ECTC.2000.853309","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853309","url":null,"abstract":"Several under bump metallization (UBM) schemes using CuNi alloys as the solderable layer were investigated. The nickel slows down the dissolution of the UBM into the solder and the formation of intermetallics during reflow. Ni containing UBMs were fabricated and reflowed with eutectic SnAg solder balls. The solder/UBM interfaces were analysed with SEM to find out how the Ni concentration affects the reaction, and how much Ni is needed to obtain a sufficiently slow reaction rate. Reflows were also made on top of bulk substrates to study the reaction when there is an unlimited amount of CuNi available. To determine the rate of dissolution of the substrate material into solder, CuNi foils of different concentrations were immersed in pure Sn and eutectic PbSn solder baths for soldering times ranging from 30 seconds to 30 minutes. Since nickel metallizations often have high stresses, stress in the UBMs was measured by the wafer curvature method. Stress vs. Ni content plots show that while stresses increase somewhat with the Ni content, the adhesion layer under the CuNi layer has a much larger effect on the stress.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126295275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Finite element modeling of BGA packages for life prediction BGA封装寿命预测的有限元建模

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853300

G. Gustafsson, I. Guven, V. Kradinov, E. Madenci

{"title":"Finite element modeling of BGA packages for life prediction","authors":"G. Gustafsson, I. Guven, V. Kradinov, E. Madenci","doi":"10.1109/ECTC.2000.853300","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853300","url":null,"abstract":"The life-prediction analysis of an electronic package requires a sequence of critical assumptions concerning the finite element models, such as the slice model and a global model with or without a submodel. Although specifics of such analyses are available in the literature, a comparison among themselves against the same electronic package with measured life cycles does not exist. This study addresses the questions arising during the life-prediction analysis by considering two particular packages with different geometric and material compositions. Solder joint reliability analyses for each of the packages are performed by constructing the following commonly accepted finite element models: (1) nonlinear slice model, (2) nonlinear global model with linear super elements, (3) linear global model with nonlinear submodel, (4) nonlinear global model with a nonlinear submodel, and (5) nonlinear global model. In the global analysis with a submodel, the displacement fields obtained from the global analysis are extrapolated for different temperatures and applied as boundary conditions in the submodel of the solder joint with a refined mesh. In the nonlinear analysis, four thermal cycles are sufficient to achieve a stable hysteresis loop. The volume-weighted plastic work density and the characteristic life are calculated in all cases. The life predictions based on widely accepted Darveaux empirical constants are compared to experimental measurements. This study helps to identify the effects of certain modeling assumptions on characteristic life predictions.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"20 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126011835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 66

Recent advances on a wafer-level flip chip packaging process 晶圆级倒装晶片封装工艺的最新进展

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853127

Q. Tong, B. Ma, E. Zhan, A. Savoca, L. Nguyen, C. Quentin, S. Luo, H. Li, L. Fan, C. Wong

{"title":"Recent advances on a wafer-level flip chip packaging process","authors":"Q. Tong, B. Ma, E. Zhan, A. Savoca, L. Nguyen, C. Quentin, S. Luo, H. Li, L. Fan, C. Wong","doi":"10.1109/ECTC.2000.853127","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853127","url":null,"abstract":"In the last few years, flip chip technology has been increasingly employed in a variety of applications in the microelectronics industry. Comparing to conventional wirebonding technology, flip chip provides lower profile, faster signal transfer, and higher I/O density. One of the key materials used in flip chip is the underfill encapsulant, which enhances the reliability of the flip chip device by more than an order of magnitude. Currently, underfilling is carried out at the package level, e.g., each chip has to be processed individually after solder reflow. The encapsulant has to be post-cured subsequently off-line. The slow underfilling process becomes a bottleneck in the high volume manufacturing of flip chip. A joint venture program, sponsored by the Advanced Technology Program (ATP), was formed to explore the next paradigm shift in flip chip packaging technology, namely, processing underfill at the wafer level. In this process, the underfill is deposited on the wafer prior to dicing. At the assembly stage, the singulated die is processed as in standard flip chip reflow operations. The main difference is that the pre-coated underfill with built-in flux will cure concurrently with the reflow of the solder, allowing both electrical and structural interconnection to be achieved simultaneously. Therefore, this wafer level underfill process offers much potential in terms of reduced production time and increased throughput. The process will be directly suitable for high volume production using the existing assembly infrastructure, lowering the cost of implementation. In this paper, the technical challenges and the solutions for both materials development and process verification in this program will be discussed.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121079205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Triple-chip stacked CSP 三芯片堆叠CSP

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853182

Y. Fukui, Y. Yano, H. Juso, Yuji Matsune, K. Miyata, A. Narai, Y. Sota, Y. Takeda, K. Fujita, M. Kada

引用次数: 27

Conductive ink for through hole application 通孔用导电油墨

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI: 10.1109/ECTC.2000.853268

A. Xiao, Q. Tong, A. Savoca, R. Frentzel, M. C. Rendle, H. Van Oosten

{"title":"Conductive ink for through hole application","authors":"A. Xiao, Q. Tong, A. Savoca, R. Frentzel, M. C. Rendle, H. Van Oosten","doi":"10.1109/ECTC.2000.853268","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853268","url":null,"abstract":"Silver Through Hole (STH) technology describes a method of creating an electrical interconnect between the top and bottom sides of a printed circuit board. STH production has gained and continues to rapidly gain acceptance worldwide due to its low-cost, reliable and environmental friendly process. The detailed process for through hole connection is described in this paper. Even though the technology necessary to produce STH boards is mature, the performance of current through hole ink relies on different printed circuit board (PCB). The stability of electrical conductivity on exposure to solder baths or to thermal cycling is a predominant issue. This problem is associated with different metal fillers, resin systems and PCB types. For example, the electrical resistance of the ink on FR2 substrate gradually increases after each solder bath dip. Fundamental study has been conducted on the root cause of the hole resistance drifts after solder bath. TMA and DMA have been used to characterize CTE and curing performance of the ink and PCB substrates. The failure mechanism has been proposed and confirmed by designed experiments. Experimental results demonstrated that a hole resistance drift on FR2 substrate is caused by several factors. First, the higher thermal expansion of the substrate itself stretches the coating layer. Secondly, the continued curing makes the resin matrix fixed at higher temperature. The final factor is the CTE mismatch between the conductive ink and PCB substrate.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15