2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)最新文献

{"title":"Novel, high density R/C terminating networks","authors":"L. Schaper, R. Ulrich, C. Gross, P. Parkerson","doi":"10.1109/ECTC.2000.853421","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853421","url":null,"abstract":"Integrated 100 pF/50 /spl Omega/ R/C terminators with an 0402 footprint were designed, fabricated and evaluated on Si and glass substrates. These structures consisted of compound anodized Ta capacitors and a Ta metal resistor, and required only two mask steps, two metal layers, no vias, and patterning by wet etching. The component values can be adjusted without having to change the size of the terminators or make new masks because the capacitance may be modified by changing the anodization voltage and the resistance by changing the Ta thickness. Each terminator showed classic R/C behavior near expected values. Of the 600 terminators fabricated on two 5 inch wafers, only two were defective due to capacitor shorts and none due to resistor faults. Further size reductions are possible; these devices could be integrated as 8, 32 or 64-wide arrays for bus termination. The device density is limited only by a reasonable I/O pitch for CSP-like attachment.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116810061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chip-scale packaging of power devices and its application in integrated power electronics modules","authors":"Xingsheng Liu, Xiukuan Jing, G. Lu","doi":"10.1109/ECTC.2000.853179","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853179","url":null,"abstract":"We present a power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional integrated power electronics modules (IPEMs). The chip-scale packaging structure, termed Die Dimensional Ball Grid Array (D/sup 2/BGA), eliminates wise bonds by using stacked solder bumps to interconnect power chips. D/sup 2/BGA package consists of a power chip, inner solder bumps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniature possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultra-low profile packaging. Electrical tests show that the V/sub CE/(sat) and on-resistance of the D/sup 2/BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device's wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D/sup 2/BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"808 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123918933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lens-less semiconductor optical amplifier (SOA) modules using laser welding techniques","authors":"M.W. Park, J.R. Kim, S. Park, J.S. Lee, H. Kim, A. Choo, T. Kim","doi":"10.1109/ECTC.2000.853240","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853240","url":null,"abstract":"We report the high performance SOA modules made using laser welding technique. The SOA chip is DH structure and its stripe of active layer is tilted by 7/spl deg/ and facet is AR coated for low reflection of 10/sup -5/ order. We used a cylindrical type laser welding (it is 3-point welding) for fiber fixing the fiber for direct coupling. We used specially designed the components of ferrule, sleeve, and submodule. The lap welding is used in the ferrule-sleeve fixing and lap-fillet welding in sleeve-submodule the fixing is used. The welding loss is usually less than 0.5 dB after a readjustment. This method is proven to be a very simple and stable technique for direct coupling. The chip gain and far field angle are 30 dB and 160/spl times/160 respectively, and the fiber is taper lensed fiber. With the coupling loss and the welding loss of -2.2 dB/facet, we can obtain the module gain of 25 dB.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124477756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Prediction of fatigue crack initiation between underfill epoxy and substrate","authors":"D. Wu, B. Su, Y.C. Lee, M. Dunn","doi":"10.1109/ECTC.2000.853227","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853227","url":null,"abstract":"Delamination between underfill epoxy and a substrate is a critical reliability concern for flip-chip assemblies. Delamination often initiates from multimaterial interface corners, which are sites of elevated stresses, under cyclic loads during testing or operation. Most existing studies of delamination have focused on crack propagation; the presence of an existing crack is assumed, and the conditions under which it will propagate are studied. The related, but different, issue of crack initiation has received far less study. To date, no widely-accepted models of crack initiation from multimaterial interface corners under fatigue loading exist. Here we propose a first step toward establishing such a model. In this study we have used interface corner stress intensities under cyclic loading (/spl Delta/K) to correlate fatigue crack initiation at bimaterial interface corners with different far-field loadings and geometries. Fracture under cyclic loads usually initiates at the interface corner and propagates along an interface. The stress states at the interface corner drives the fatigue crack initiation process. In certain cases, crack initiation can be correlated using a critical value of the stress intensity that exists at the bimaterial interface corner in the context of a linear elastic stress analysis. The stress intensities uniquely characterize the stress state in an annular region surrounding the interface corner with a singular stress field. In order to demonstrate the use of critical stress intensities to correlate fracture initiation, we measured the number of cycles required to initiate a fatigue crack from an epoxy/steel interface corner. The preliminary results suggest that fatigue crack initiation can be correlated with critical values of the stress intensities. Furthermore, the proposed approach to correlate fatigue crack initiation can be coupled with existing approaches to correlate fatigue crack propagation, thus resulting in a tool for complete lifecycle analysis.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125993142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The effect of temperature cycling on fiber-solder-ferrule joints in laser module packaging","authors":"Wei Cheng, M. Sheen, J. Kuang, J.C. Chen, G.L. Wang, S.C. Wang, H.L. Chang, C. Wang, C.M. Wang","doi":"10.1109/ECTC.2000.853412","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853412","url":null,"abstract":"The thermally-induced fiber alignment shifts of fiber-solder-ferrule (FSF) joints in laser module packaging have been studied experimentally and numerically. Direct measurements of the metallographic photos with and without temperature cycling, fiber displacement shifts of up to a 0.8 /spl mu/m were found after undergoing 500 temperature cycles. Experimental results show that the fiber shifts increase as the temperature cycle number and the initial fiber eccentric offset increase. The major cause of fiber shift may come from the plastic solder yielding introduced by the thermal stress variation and the redistribution of the residual stresses during temperature cycling. A finite-element method (FEM) analysis was performed to evaluate the variation of thermal stresses, the distribution of residual stresses, and fiber shifts of the FSF joints. Experimental measurements were in reasonable agreement with the numerical calculations. Both results indicate that the initial offset introduced in the fiber soldering process is a key parameter in causing the thermally-induced fiber shift of FSF joints in laser module packaging. The fiber shift, and hence fiber alignment shift under temperature cycling tests can be reduced significantly if the fiber can be located close to the center of the ferrule.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124781220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on rate-dependent behaviors of underfills based on two-phase composites","authors":"Haiying Wang, Z. Qian, Minfu Lu, Sheng Liu, Jiali Wu, C. Wong","doi":"10.1109/ECTC.2000.853175","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853175","url":null,"abstract":"Underfills' properties are very important for the reliability of flip chip packages. As epoxy based materials, underfills show obvious rate-dependent behaviors under mechanical loading. However, studies on the rate-dependent behavior of underfills have been rarely reported, In this paper, the rate-dependent strain-stress behavior of underfills is studied based on two-phase composite assumption. A micromechanical method is employed to predict the overall strain-stress behavior of underfills. Results show good agreement between the predicted data and experimental data.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129707911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Curriculum restructure to answer critical needs in packaging for energy efficiency/renewable energy systems, wireless, and mixed-signal systems areas","authors":"W. Brown, A. Elshabini, S. Ang, J. Balda, F. Barlow, R. Coubillion, A. Malshe, R. Malstrom, A. Mantooth, T. Martin, H. Naseem, R. Jones, W. Waite, R. Brown, N. Schmitt, D. Nutter, G. Salamo, L. Schaper, W. Schmidt, R. Selvam, S. Singh, K. Olejniczak, R. Ulrich, J. Yeargan, E. Yaz, W. White","doi":"10.1109/ECTC.2000.853338","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853338","url":null,"abstract":"The Electrical Engineering Department at University of Arkansas has been building considerable strength in Energy Efficiency/Renewable Energy Systems, Mixed-Signal, and Wireless Packaging areas. This effort is in coordination with critical other Departments within the College of Engineering; specifically Industrial Engineering and Mechanical Engineering Departments, in addition to the Physics Department within the College of Arts and Science. The High Density Electronics Center (HiDEC), established in 1992 with DARPA funds to conduct research on advanced electronic packaging technologies, enables the educators to interact within the various disciplines to achieve the set objectives of packaging in these areas. The paper will outline the mission of each area, the vision and objectives of the administration, the technical issues to be addressed, the technological challenges and barriers for the Department to face and overcome to make this vision a true reality, and the curriculum restructure. The paper will also outline how critical these strategic areas are for a national academic institution recognition and fulfillment of critical needs for our nation's global competitiveness.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128222681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Eutectic Sn-Ag solder bump process for ULSI flip chip technology","authors":"H. Ezawa, M. Miyata, S. Honma, H. Inoue, T. Tokuoka, J. Yoshioka, M. Tsujimura","doi":"10.1109/ECTC.2000.853307","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853307","url":null,"abstract":"The novel developed Sn-Ag eutectic solder bump process provides several advantages over conventional solder bump process schemes. Steep wall bumps as plated were fabricated using the nega-type photo resist with a thickness of more than 50 /spl mu/m by one time spin coating. This improves productivity for mass production. The 2-step electroplating process was performed using separate plating reactors for Ag and Sn. The eutectic Sn-Ag alloy bumps were easily obtained by annealing the metal stacks with Sn layer on Ag layer sequentially electroplated. This electroplating process does not need to strict control of the content ratio of Ag to Sn in an alloy plating solution even with increasing electroplating depositions. The novel developed process gives the within-wafer uniformity of the bump height as reflowed of less than 10% and of the Sn-Ag alloy composition as reflowed of less than /spl plusmn/0.5wt.%Ag, analyzed by ICP spectrometry. Shear strength measurements were performed to known thermal stability for the structure of Cu pads/Ti/Ni/Pd/Sn-Ag eutectic solder stack. In the case of the Ti (100 nm)/Ni (300 nm)/Pd (50 nm) barrier metal stacks, the shear strength after 5 times annealing in N2 ambience at 260/spl deg/C decreased to 70% than that as reflowed. As the Ti becomes thicker in the Ti/Ni/Pd metal stack, shear strengths are improved. Comparing the structure of Cu/Ti/Ni/Pd/Sn-Ag eutectic solder with the case of Ta/Ti/Ni/Pd and Nb/Ti/Ni/Pd barrier metal stacks. The analysis results of Auger spectrometry show that Sn diffusion into Cu to form Cu-Sn alloy was observed only in Cu/Ta/Ti/Ni/Pd barrier metal stacks. These results suggest that the same Ti/Ni/Pd barrier metal stack as used in Sn-Pb solder bump and Au bump is viable for ULSIs with Cu interconnects.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129289879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel jet fluxing application for advanced flip chip and BGA/CGA packages","authors":"R. Master, A. Dubey, Martin Guardado, O.T. Ong, B. Donges, F. Okada","doi":"10.1109/ECTC.2000.853324","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853324","url":null,"abstract":"In many applications today involving flip chip, ball grid array and column grid array technologies; flux application is an important process parameter. Dispensing flux requires reproducibility of dispense weight so that amount of flux residue can be controlled. Flux residue causes defects such as voids and delamination when flip chip is underfilled. This problem is magnified with the size of the die and future applications involving finer pitches. Cleaning the flux residue also becomes more difficult with the increase in die size and reduction of bump pitch. The control of weight is also essential when no clean processes are used. The residue left may also contribute to degradation in reliability by leakage as well as contribute to voids in the underfill. The paper shows an application such as solder column interposer where a column grid array interposer is attached to a package, the gap between the package and the interposer is very small. In such cases, it is not possible to clean and therefore use of no clean flux becomes imperative. In addition, the area that needs to be covered is quite large e.g. 31 mm./spl times/31 mm. Because of such large area, it is not possible to use conventional methods such as brushing or dipping. These methods are also slow and not amenable to high volume applications. Process development was carried out by developing fluxes with suitable viscosity. An additional need was to provide versatility to accommodate different flip chip and column footprints. This process is now fully programmable so that various packages can be used without having to retool the equipment. We have developed a repeatable process that accurately controls the weight of the flux. We will describe a new high volume application using jet fluxer. This fluxing application has been developed for flip chip, ball grid array and column grid array applications. We will describe the development of the jet fluxer where flux is atomized and sprayed. During the development major hurdles were overcoming the surface tension variations of different packages and development of flux with correct viscosity. The process initially had the capability of only spraying very small number of units due to limitations of the nozzle. The nozzle limitations also limited the ability to control the weight. We will show how these problems have been overcome. The process has been implemented in high volume production successfully for both flip chip and column grid array applications.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131061746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of reliability and process ability for preset underfill sheet material as future standard flip chip packaging process","authors":"H. Noro, M. Mizutani, M. Kuwamura, H. Usui, S. Ito","doi":"10.1109/ECTC.2000.853170","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853170","url":null,"abstract":"Process technology in flip chip assembly is an important factor in considering the package reliability, cost reduction and stability of mass production. A novel flip chip packaging technology using non-conductive underfill resin sheet was developed. This new technology is no-flux flip chip packaging technology which eliminates the flux applying and cleaning process in current liquid underfill resin with dispensing system. It has a lot of potential to make the packaging process simpler and reduce handling difficulty compared with liquid underfill dispensing process. Additionally, it makes moisture related reliability performance higher because this underfill resin sheet introduces an epoxy resin with phenol curing system. In this paper, we studied the process ability and reliability on two kinds of packaging processes with non-conductive underfill resin sheets. The higher stress reliability and productivity was shown with the proper underfill resin component and packaging process.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"53 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132026651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}