2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)最新文献

{"title":"Single mode fiber MT-RJ SFF transceiver module using optical sub assembly with a new shielded silicon optical bench","authors":"M. Iwase, T. Nomura, A. Izawa, H. Mori, S. Tamura, T. Shirai, T. Kamiya","doi":"10.1109/ECTC.2000.853238","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853238","url":null,"abstract":"Recently, strong demands for compactness and drastic cost reduction of optical transceivers are arising. Small Form Factor (SFF) optical transceivers are expected to meet these demands. The new conceptual optical module based on v-grooved silicon optical bench (SiOB) technology, that enables a passive alignment of optical fibres and optical devices is also expected to reduce the cost drastically. MT-RJ SFF optical transceivers require this new packaging technique because the distance between input and output optical axes is shorter than conventional transceivers. However, crosstalk between a transmitter and a receiver is a big issue to be solved because the distance between optical axes of the Laser diode (LD) and the Photo diode (PD) is only 0.75 mm. Especially, it is difficult to reduce the crosstalk in a SiOB because large electromagnetic coupling exists due to the conductivity of a silicon substrate. In this paper, a newly developed, low crosstalk optical sub assembly (OSA) with a single mode fiber MT-RJ receptacle and the SFF transceiver module using it are reported. We have analyzed a mechanism of electrical crosstalk in a SiOB and developed a shield structure to reduce it. The crosstalk in the OSA with shielded SiOB was reduced over 20 dB compared to the unshielded SiOB.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130707218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Qualification and reliability tests: What are we doing and why?","authors":"R. A. Munroe","doi":"10.1109/ECTC.2000.853425","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853425","url":null,"abstract":"The semiconductor industry and its customers perform component qualification tests and reliability tests that are reasonably similar if not the same due to the standards in the industry and tradition. Some of the tests are not reliability tests, but robustness tests and the term reliability is often misused. As semiconductor technology has advanced and electronic packaging has changed the tests and criteria have not been changed at the same rate. The spectrum of applications has grown so that in some cases the tests are overly stringent or testing for the wrong failure mechanisms. In other cases the tests do not adequately reflect the level or length of time necessary to ensure successful applications. This paper will attempt to challenge the conventional tests and acceptance of those tests and to encourage the reader to look at semiconductor tests in a different light. A proposed method is made to use the tests in place in a more productive manner.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131077628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of simulation methodology on solder joint crack growth correlation","authors":"R. Darveaux","doi":"10.1109/ECTC.2000.853299","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853299","url":null,"abstract":"A generalized solder joint fatigue life model for surface mount packages was previously published by the author. The model is based on correlation to measured crack growth data on BGA joints during thermal cycling. It was subsequently discovered by Anderson et. al. that the ANSYS/sup TM/ 5.2 finite element code used in the model had an error in its method for calculating plastic work. It was shown that significant error in life prediction could result by using a recent version of the code where the bug has been fixed. The error comes about since the original crack growth constants were derived based on plastic work calculations that had the bug. In this paper, crack initiation and growth constants are recalculated using ANSYS/sup TM/ 5.6. In addition, several other model related issues are explored with respect to the crack growth correlations. For example, 3D slice models were compared to quarter symmetry models. Anand's constitutive model was compared with Darveaux's constitutive model. It was shown that the crack growth rate dependence on strain energy density always had an exponent of 1.10+/-0.15. This is in the range of the original correlation, so the accuracy of relative predictions should still be within+/-25%. However, the accuracy of absolute predictions could be off by a factor of 7 in the worst case, if the analyst uses a modeling procedure that is not consistent with that used for the crack growth correlation. The key to good accuracy is to maintain consistency in the modeling procedure.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability characterization in Ultra CSP/sup TM/ package development","authors":"H. Yang, P. Elenius, S. Barrett, C. Schneider, J. Leal, R. Moraca, R. Moody, Y. Kweon, Deok-Hoon Kim, D. Patterson, T. Goodman","doi":"10.1109/ECTC.2000.853389","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853389","url":null,"abstract":"Ultra CSP/sup TM/ is a wafer-level chip scale package developed by Flip Chip Technologies. This package provides a low cost packaging solution for various applications such as integrated passive, flash memory, DRAM, and Direct RDRAM/sup TM/ devices. This paper presents a brief update of the Ultra CSP development effort. Two design concepts were evolved in the development process and product implementation to address the requirements of different applications. Solder joint reliability of Ultra CSP was evaluated at board level under thermal cycle test. A solder joint fatigue database was generated using Weibull analysis. The effect of die size (DNP), bump standoff, substrate pad size, and solder ball size are discussed. Continued improvement in the package reliability is achieved through Design of Experiments. Issues encountered in the qualification stage are addressed in terms of accelerated test strategy, process quality control, package design, and substrate design.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133518205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Alignment considerations in packaging array-based optical interconnects and processors","authors":"A. K. Ghosh","doi":"10.1109/ECTC.2000.853411","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853411","url":null,"abstract":"Because of micron-level size of optical components in arrays used in high-speed optical interconnection or switching systems, and the large number of elements in such arrays, achieving the alignment necessary for the optical interconnect to operate correctly and reliably is a difficult task. A tool for quantitatively specifying the relative difficulty of aligning the arrays of optical components in an optical package is developed in this paper. The alignment of two rigid arrays, one of optical sources and the other of optical receptors is analyzed. The power coupling efficiency between the source and the receptor array elements is determined based on their sizes, inter-element spacing and distances, and the six possible types of random offsets that can occur owing to the positioning of the arrays. The cross-talk level is calculated. A statistical measure of the ease or difficulty with which an optical interconnect can be aligned is then determined. This measure, called the array-alignability, uses the probability of achieving a given efficiency of power transfer in spite of the random offsets. Since efficiency varies with changing component sizes, positioning tolerances, etc., the array-alignability depends upon various size and shape parameters. An optical interconnect or switching processor in which array-alignability is high has an easier task of alignment and is more tolerant of various offsets.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132333025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lead free solder paste flux evaluation and implementation in personal communication devices","authors":"A. Butterfield, V. Visintainer, V. Goudarzi","doi":"10.1109/ECTC.2000.853397","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853397","url":null,"abstract":"This paper outlines the printing and wetting experimentation and the findings of a lead free solder paste comparison, and identifies one flux vehicle capable of performing across a wide temperature range of reflow profiles. The study included a lead free alloy using three different flux vehicles. The test boards used were a copper surface finish with organic surface protection (OSP) and Ni-Au. The goal was to understand the printing performance over time and the effect of time above liquidus and peak temperatures on the wetting characteristics for each solder paste in an air and nitrogen reflow atmosphere. The volumetric data from the printing experiment revealed little difference between the pastes and determined that the wetting characteristics would carry the most weight for the decision of a lead free solder paste. The wetting results clearly showed that only one of the solders used performed well in all the reflow profiles tested, while the others exhibited wetting problems in air as the volume of printed solder decreased. The identification of one flux vehicle allowed for the manufacturing process to be optimized, and shared with other sites globally.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115375605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of low alpha emissivity system on electroplated solder bumps","authors":"A. Mistry, S. Lee, C. Enman, B. Carroll, D. Mitchell, V. Mathew, D. Weeks, M. Tucker","doi":"10.1109/ECTC.2000.853427","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853427","url":null,"abstract":"As attention to System Soft Error Rate (SSER) grows, better semiconductor design guidelines are being created. To protect sensitive transistor nodes from alpha particles emanating from trace amounts of natural occurring radioisotopes, improved shielding materials such as die coat barrier films are being used. In parallel, the demand for lower alpha emissivity materials is growing, such that semiconductor materials suppliers and packaging groups must certify their materials as being of a certain alpha emissive content. To this end, this alpha detection system continues to gain prominence, with detection capabilities down to 0.001 alpha count/cm/sup 2//hour and sample measurement sizes to 1000 square centimeters. This study outlines a method of characterization and determines capability of the continuous gas flow proportional counter.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115696874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New CBGA package with improved 2/sup nd/ level reliability","authors":"R. Pendse, B. Afshari, N. Butel, J. Leibovitz, Y. Hosoi, M. Shimada, K. Maeda, M. Maeda, H. Yonekura","doi":"10.1109/ECTC.2000.853325","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853325","url":null,"abstract":"In the present work, we have studied several improvements in the materials, structure and design of the conventional flip chip-on-ceramic single chip package aimed at increasing the 2/sup nd/ level reliability. The use of a novel ceramic substrate material (\"HITCE Ceramic\"), coupled with systematic changes in design and assembly materials resulted in an improvement of 2/sup nd/ level reliability over the conventional alumina-based ceramic ball grid array (CBGA) package by approximately one order of magnitude. In the initial testing, a strong effect of the heat spreader (lid) structure on 2/sup nd/ level reliability was seen. A careful finite element modeling (FEM) study was undertaken to understand the interaction of the package structure with 2/sup nd/ level solder joint stress. The results of the study were validated based on empirical temp cycle data and by direct solder joint strain measurements using a novel strain measurement technique. Once validated, FEM was used as a tool for optimizing the package structure, namely, the lid material and thickness, the attach material between the lid and the the ceramic substrate, and the size and location of the attachment points. To minimize the impact on thermal performance and component level reliability, the die attach material was left unchanged. The optimized package structure was subsequently fabricated and subjected to 2/sup nd/ level reliability testing. An approximately one order of magnitude improvement was seen, consistent with FEM predictions. It was necessary to ensure that the component-level reliability was not compromised as a result of the higher coefficient of thermal expansion (CTE) of the ceramic substrate material (HITCE), which presented a greater CTE mismatch between the die and substrate compared to the case of alumina ceramic. Therefore, a re-selection of the underfill material was performed and the component-level reliability with the chosen underfill material was verified through temp cycling and moisture tests (Cond B temp cyl and HAST).","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114539527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interfacial degradation of epoxy-coated silicon nitride","authors":"Jongwoon Park, D. Harlow","doi":"10.1109/ECTC.2000.853184","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853184","url":null,"abstract":"A silicon (Si) wafer passivated with a nitride film, fabricated by low-pressure chemical vapor deposition, and coated with epoxy was used as a test specimen to characterized the interfacial degradation. The highly accelerated stress test (HAST) conditions were 121/spl deg/C and unsaturated 100% relative humidity. Optical microscopy was used to monitor the growth of damage as a function of time. Results of electron microscopy and X-ray photoelectron spectrometry (XPS) indicate that two different failure modes exist at the interface.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116248126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications","authors":"A. Mirza","doi":"10.1109/ECTC.2000.853231","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853231","url":null,"abstract":"The ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate is becoming a critical issue for a variety of semiconductor applications. For CMOS devices this technology will be applied for chip-scale packaging and also for advanced 3-D interconnect processes. In the microelectromechanical systems (MEMS) arena, accurate alignment of two silicon micromachined wafers enables the design of more advanced MEMS devices and aggressive die shrinks of existing products. In this paper we discuss the advantages and disadvantages of various substrate-to-substrate alignment techniques including infrared, through wafer via, inter-substrate optical and wafer backside alignment methods. We also report on a new approach to wafer-to-wafer alignment that relies on precision alignment positioning systems to register and align wafers with one micron or better precision. Test results from this wafer-to-wafer alignment system demonstrate that one micron alignment accuracy can be routinely obtained. This new wafer-level alignment and bonding technique is particularly well suited for high-volume manufacturing due to the long-term stability of the precision alignment positioning system. This paper gives a brief overview of some typical uses of aligned wafer-level bonding for chip-scale, 3-D interconnect and MEMS applications.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123574450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}