R. Pendse, B. Afshari, N. Butel, J. Leibovitz, Y. Hosoi, M. Shimada, K. Maeda, M. Maeda, H. Yonekura
{"title":"新的CBGA封装,提高了2/sup和/ level的可靠性","authors":"R. Pendse, B. Afshari, N. Butel, J. Leibovitz, Y. Hosoi, M. Shimada, K. Maeda, M. Maeda, H. Yonekura","doi":"10.1109/ECTC.2000.853325","DOIUrl":null,"url":null,"abstract":"In the present work, we have studied several improvements in the materials, structure and design of the conventional flip chip-on-ceramic single chip package aimed at increasing the 2/sup nd/ level reliability. The use of a novel ceramic substrate material (\"HITCE Ceramic\"), coupled with systematic changes in design and assembly materials resulted in an improvement of 2/sup nd/ level reliability over the conventional alumina-based ceramic ball grid array (CBGA) package by approximately one order of magnitude. In the initial testing, a strong effect of the heat spreader (lid) structure on 2/sup nd/ level reliability was seen. A careful finite element modeling (FEM) study was undertaken to understand the interaction of the package structure with 2/sup nd/ level solder joint stress. The results of the study were validated based on empirical temp cycle data and by direct solder joint strain measurements using a novel strain measurement technique. Once validated, FEM was used as a tool for optimizing the package structure, namely, the lid material and thickness, the attach material between the lid and the the ceramic substrate, and the size and location of the attachment points. To minimize the impact on thermal performance and component level reliability, the die attach material was left unchanged. The optimized package structure was subsequently fabricated and subjected to 2/sup nd/ level reliability testing. An approximately one order of magnitude improvement was seen, consistent with FEM predictions. It was necessary to ensure that the component-level reliability was not compromised as a result of the higher coefficient of thermal expansion (CTE) of the ceramic substrate material (HITCE), which presented a greater CTE mismatch between the die and substrate compared to the case of alumina ceramic. Therefore, a re-selection of the underfill material was performed and the component-level reliability with the chosen underfill material was verified through temp cycling and moisture tests (Cond B temp cyl and HAST).","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"New CBGA package with improved 2/sup nd/ level reliability\",\"authors\":\"R. Pendse, B. Afshari, N. Butel, J. Leibovitz, Y. Hosoi, M. Shimada, K. Maeda, M. Maeda, H. Yonekura\",\"doi\":\"10.1109/ECTC.2000.853325\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the present work, we have studied several improvements in the materials, structure and design of the conventional flip chip-on-ceramic single chip package aimed at increasing the 2/sup nd/ level reliability. The use of a novel ceramic substrate material (\\\"HITCE Ceramic\\\"), coupled with systematic changes in design and assembly materials resulted in an improvement of 2/sup nd/ level reliability over the conventional alumina-based ceramic ball grid array (CBGA) package by approximately one order of magnitude. In the initial testing, a strong effect of the heat spreader (lid) structure on 2/sup nd/ level reliability was seen. A careful finite element modeling (FEM) study was undertaken to understand the interaction of the package structure with 2/sup nd/ level solder joint stress. The results of the study were validated based on empirical temp cycle data and by direct solder joint strain measurements using a novel strain measurement technique. Once validated, FEM was used as a tool for optimizing the package structure, namely, the lid material and thickness, the attach material between the lid and the the ceramic substrate, and the size and location of the attachment points. To minimize the impact on thermal performance and component level reliability, the die attach material was left unchanged. The optimized package structure was subsequently fabricated and subjected to 2/sup nd/ level reliability testing. An approximately one order of magnitude improvement was seen, consistent with FEM predictions. It was necessary to ensure that the component-level reliability was not compromised as a result of the higher coefficient of thermal expansion (CTE) of the ceramic substrate material (HITCE), which presented a greater CTE mismatch between the die and substrate compared to the case of alumina ceramic. Therefore, a re-selection of the underfill material was performed and the component-level reliability with the chosen underfill material was verified through temp cycling and moisture tests (Cond B temp cyl and HAST).\",\"PeriodicalId\":410140,\"journal\":{\"name\":\"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. 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New CBGA package with improved 2/sup nd/ level reliability
In the present work, we have studied several improvements in the materials, structure and design of the conventional flip chip-on-ceramic single chip package aimed at increasing the 2/sup nd/ level reliability. The use of a novel ceramic substrate material ("HITCE Ceramic"), coupled with systematic changes in design and assembly materials resulted in an improvement of 2/sup nd/ level reliability over the conventional alumina-based ceramic ball grid array (CBGA) package by approximately one order of magnitude. In the initial testing, a strong effect of the heat spreader (lid) structure on 2/sup nd/ level reliability was seen. A careful finite element modeling (FEM) study was undertaken to understand the interaction of the package structure with 2/sup nd/ level solder joint stress. The results of the study were validated based on empirical temp cycle data and by direct solder joint strain measurements using a novel strain measurement technique. Once validated, FEM was used as a tool for optimizing the package structure, namely, the lid material and thickness, the attach material between the lid and the the ceramic substrate, and the size and location of the attachment points. To minimize the impact on thermal performance and component level reliability, the die attach material was left unchanged. The optimized package structure was subsequently fabricated and subjected to 2/sup nd/ level reliability testing. An approximately one order of magnitude improvement was seen, consistent with FEM predictions. It was necessary to ensure that the component-level reliability was not compromised as a result of the higher coefficient of thermal expansion (CTE) of the ceramic substrate material (HITCE), which presented a greater CTE mismatch between the die and substrate compared to the case of alumina ceramic. Therefore, a re-selection of the underfill material was performed and the component-level reliability with the chosen underfill material was verified through temp cycling and moisture tests (Cond B temp cyl and HAST).