Ultra CSP/sup TM/封装开发中的可靠性表征

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) Pub Date : 2000-05-21 DOI:10.1109/ECTC.2000.853389

H. Yang, P. Elenius, S. Barrett, C. Schneider, J. Leal, R. Moraca, R. Moody, Y. Kweon, Deok-Hoon Kim, D. Patterson, T. Goodman

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引用次数: 7

摘要

Ultra CSP/sup TM/是由Flip chip Technologies开发的晶圆级芯片规模封装。该封装为集成无源、闪存、DRAM和直接RDRAM/sup TM/器件等各种应用提供了低成本封装解决方案。本文简要介绍了Ultra CSP开发工作的最新进展。在开发过程和产品实现中发展了两个设计概念，以解决不同应用程序的需求。通过热循环试验，在板级评价了Ultra CSP焊点的可靠性。采用威布尔分析方法建立了焊点疲劳数据库。讨论了模具尺寸、凸点间距、衬底衬垫尺寸和焊料球尺寸的影响。通过实验设计，实现了封装可靠性的持续提高。在确认阶段遇到的问题是根据加速测试策略、过程质量控制、封装设计和基板设计来解决的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Reliability characterization in Ultra CSP/sup TM/ package development

Ultra CSP/sup TM/ is a wafer-level chip scale package developed by Flip Chip Technologies. This package provides a low cost packaging solution for various applications such as integrated passive, flash memory, DRAM, and Direct RDRAM/sup TM/ devices. This paper presents a brief update of the Ultra CSP development effort. Two design concepts were evolved in the development process and product implementation to address the requirements of different applications. Solder joint reliability of Ultra CSP was evaluated at board level under thermal cycle test. A solder joint fatigue database was generated using Weibull analysis. The effect of die size (DNP), bump standoff, substrate pad size, and solder ball size are discussed. Continued improvement in the package reliability is achieved through Design of Experiments. Issues encountered in the qualification stage are addressed in terms of accelerated test strategy, process quality control, package design, and substrate design.

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2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

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