Recent advances on a wafer-level flip chip packaging process

Abstract

In the last few years, flip chip technology has been increasingly employed in a variety of applications in the microelectronics industry. Comparing to conventional wirebonding technology, flip chip provides lower profile, faster signal transfer, and higher I/O density. One of the key materials used in flip chip is the underfill encapsulant, which enhances the reliability of the flip chip device by more than an order of magnitude. Currently, underfilling is carried out at the package level, e.g., each chip has to be processed individually after solder reflow. The encapsulant has to be post-cured subsequently off-line. The slow underfilling process becomes a bottleneck in the high volume manufacturing of flip chip. A joint venture program, sponsored by the Advanced Technology Program (ATP), was formed to explore the next paradigm shift in flip chip packaging technology, namely, processing underfill at the wafer level. In this process, the underfill is deposited on the wafer prior to dicing. At the assembly stage, the singulated die is processed as in standard flip chip reflow operations. The main difference is that the pre-coated underfill with built-in flux will cure concurrently with the reflow of the solder, allowing both electrical and structural interconnection to be achieved simultaneously. Therefore, this wafer level underfill process offers much potential in terms of reduced production time and increased throughput. The process will be directly suitable for high volume production using the existing assembly infrastructure, lowering the cost of implementation. In this paper, the technical challenges and the solutions for both materials development and process verification in this program will be discussed.