2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)最新文献

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Feasibility of surface activated bonding for ultra-fine pitch interconnection-a new concept of bump-less direct bonding for system level packaging 超细间距互连表面活化键合的可行性——系统级封装无凸点直接键合的新概念
T. Suga
{"title":"Feasibility of surface activated bonding for ultra-fine pitch interconnection-a new concept of bump-less direct bonding for system level packaging","authors":"T. Suga","doi":"10.1109/ECTC.2000.853235","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853235","url":null,"abstract":"In the present study a method of ultra-high density interconnection, the surface activation (SAB) method is introduced. Also for the next generation of packaging, which might bridge to global interconnection on chip, a concept of bump-less bonding is proposed. The bumpless bonding will be especially suitable and inevitable for ultra-high density interconnection when it will convert the range of /spl mu/m size. For such bonding requires at the same time, combinations of a ultra-thin chip and a flexible substrate. The surface activated bonding method enables the metals and non-metallic materials to be bonded at room temperature only by contact. Some fundamental experiments and preliminary results of examination of the feasibility of the method for Cu and Cu direct bonding are presented.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116057545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Selecting methods for packing, shipping, and handling of low cost good die 选择低成本优质模具的包装、运输和处理方法
C.E. Gutentag, R. Sierra
{"title":"Selecting methods for packing, shipping, and handling of low cost good die","authors":"C.E. Gutentag, R. Sierra","doi":"10.1109/ECTC.2000.853257","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853257","url":null,"abstract":"Continuing market demands for electronic products, which are both smaller and lighter, while offering more features and greater reliability at less cost are driving manufacturers to evaluate and restructure their product designs and manufacturing processes to obtain increased throughputs coupled with higher yields. Substituting low cost bare die products for much larger, heavier and more expensive packaged IC products (e.g., PLCCs, SOICs, QFPs and the like) is a major move toward an effective response to these market demands. This paper presents the results of industry studies and surveys to set forth in detail the alternative forms of die packing and handling methods available for use. In addition, criteria are offered for selecting one or more methods best suited to each of the specific manufacturing processes being considered for use.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A compact, low-cost WDM transceiver for the LAN 一种用于局域网的紧凑、低成本的WDM收发器
Brian E. Lemoff, L. Buckman, Andrew, Schmit, D. Dolfi
{"title":"A compact, low-cost WDM transceiver for the LAN","authors":"Brian E. Lemoff, L. Buckman, Andrew, Schmit, D. Dolfi","doi":"10.1109/ECTC.2000.853237","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853237","url":null,"abstract":"As the bandwidth requirements of local area networks (LANs) continue to increase, ever-faster fiber-optic links will be required in the backbones which aggregate the traffic of many users. A need has emerged for low-cost 10-Gb/s fiber-optic links in LAN backbones, prompting the IEEE to begin work on a standard for \"10-Gigabit Ethernet\". To take advantage of the large installed base of multimode optical fiber, as well as low-cost electronics and electrical interconnect technologies, a wavelength-division-multiplexed (WDM) fiber-optic module has been proposed in which four data channels, each transmitting at a data rate of 2.5 Gb/s on a different wavelength, are carried over a single fiber. In this paper, a fully integrated transceiver is described in which four lasers, four detectors, a wavelength multiplexer, a wavelength demultiplexer, and all necessary electronics are contained within a duplex-connectorized module. The component technologies that enable the transceiver to be compact and low-cost are also described.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124894758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Packaging technology for high performance CMOS server Fujitsu GS8900 富士通GS8900高性能CMOS服务器封装技术
A. Fujisaki, M. Suzuki, H. Yamamoto
{"title":"Packaging technology for high performance CMOS server Fujitsu GS8900","authors":"A. Fujisaki, M. Suzuki, H. Yamamoto","doi":"10.1109/ECTC.2000.853275","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853275","url":null,"abstract":"Corresponding to high performance single-chip CPUs adopting 0.18 um process and copper wiring, high density wiring and multi terminal MCMs, on which the CPU and large capacity second caches can be mounted up to 4 pairs, have been newly developed. As for LSIs, bare chips are directly mounted on MCM substrates with 153 um pitch high density area bumps. The maximum LSI terminal count is more than 10,000. LSIs are connected to one another by multi layer high density fine pitch wiring, which are all made of copper and formed in thin films of MCM substrates. The supporting technologies, such as a high density multi terminal connector for the MCM, and a multi layer system mother board of high speed signal transmission correspondence where 16 CPUs and 64 GB main memories can be mounted for a maximum configuration, have been developed. Meanwhile, two kinds of newly developed lead free solders are applied in the system packaging considering of the environment protection. The following two methods have been developed in cooling technique. The high performance thermosyphon has been developed and adopted in the general air-cooled system. Moreover, in order to draw out the performance to its maximum by using the characteristics of CMOS LSI, a low temperature liquid cooling method, using a coolant around 0 degrees C, has been newly adopted to practical use in the large-scale system. With the liquid cooling scheme, not only the installation and maintainability are realized being equal to that for air-cooling, but also high reliability is achieved by a redundant cooling system that cools two or more MCMs.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124944001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Development of flex stackable carriers 柔性可堆叠载体的研制
H. Isaak, P. Uka
{"title":"Development of flex stackable carriers","authors":"H. Isaak, P. Uka","doi":"10.1109/ECTC.2000.853181","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853181","url":null,"abstract":"CSP's and /spl mu/BGA's are becoming more common in the market place and present new challenges for stacking of devices. An investigation into possible methods of stacking these devices was undertaken. New materials such as z-axis epoxies and combination flux/underfill epoxies were considered as well as the possibilities of adhesiveless copper on flex for fine line etching. This paper describes the basic approach and the results of combining the new technologies into a versatile and novel stacking approach.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123127392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Wire pull on fine pitch pads: an obsolete test for first bond integrity 细间距衬垫上的拉丝:一种过时的第一键完整性测试
V. Sundararaman, D. Edwards, W.E. Subido, H.R. Test
{"title":"Wire pull on fine pitch pads: an obsolete test for first bond integrity","authors":"V. Sundararaman, D. Edwards, W.E. Subido, H.R. Test","doi":"10.1109/ECTC.2000.853187","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853187","url":null,"abstract":"This work focuses on the validity and applicability of the wire pull test being used as a measure of first bond integrity of wire bonds on fine pitch pads used in advanced silicon technology devices. The effect of geometry of the wire bond is studied by considering variations in the angle of force application during the wire pull test and the presence of nonintermetallic region (de-bonds) created by a probe mark under the ball. This paper does not address the effects of the silicon-level interconnect structure underneath the bond-pads, i.e., it is assumed that the underlying structure is defect-free, and the layers of interconnect metal and interlayer dielectric (ILD) are modeled along with the silicon as a smeared homogeneous material. Experimental data that corroborate the findings from the finite element analyses are also presented. Results from this work indicate that if the wire pull test is applied for smaller ball diameters, some incidence of unconventional failure mechanisms, such as cohesive failure of the ILD, is to be expected and allowed. A wire pull should only be considered a failure if the ball lifts and shows poor intermetallic formation or if the wire pull fails at a pull-force substantially below the \"norm\" for that ball diameter.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122738963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Failure mechanisms of flip chip DCA assembly using eutectic solder 使用共晶焊料的倒装DCA组件的失效机制
Q. Tan, Rebecca Cole, A. Mistry, C. Beddingfield
{"title":"Failure mechanisms of flip chip DCA assembly using eutectic solder","authors":"Q. Tan, Rebecca Cole, A. Mistry, C. Beddingfield","doi":"10.1109/ECTC.2000.853120","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853120","url":null,"abstract":"Reliability performance is still the major concern for flip chip interconnection. While solder fatigue is believed to be the contributing factor for packaging failure and is the most widely studied for flip chip soldering, experimental work in this study find out solder fatigue itself is seldom the driving force for early failure. With the introduction of underfill, failures solely due to solder fatigue usually have a cycling life that is much longer than the required failure cycle. It is the other failure modes that result in early failure. This paper analyzed the major failure sources for flip chip assembly using eutectic solder. These failure mechanisms could usually resulted in early failure for the assembly. Failure mechanisms presented in this study include: underfill void, underfill delamination, underfill cracking, die cracking (horizontal and vertical), substrate cracking, and passivation crack or delamination. Discussion will also be given on how to avoid these issues.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123791974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The solder joint and runner metal reliability of wafer-level CSP (Omega-CSP) 晶圆级CSP (Omega-CSP)的焊点和流道金属可靠性
I. Kang, Jong-heon Kim, I. S. Park, Ki-Rok Hur, Soon-Jin Cho, H. Han, Jin Yu
{"title":"The solder joint and runner metal reliability of wafer-level CSP (Omega-CSP)","authors":"I. Kang, Jong-heon Kim, I. S. Park, Ki-Rok Hur, Soon-Jin Cho, H. Han, Jin Yu","doi":"10.1109/ECTC.2000.853124","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853124","url":null,"abstract":"Wafer-level Chip Size Package (Wafer Level CSP)s are competing with normal CSPs because they provide the benefits of real chip size package with low manufacturing cost. However, solder joint and runner metal reliability in board level are still critical to the acceptance of WLCSP as an alternative package. In Hyundai Electronics, Wafer-Level CSP without underfill, called Omega-CSP, has been developed for a high speed DRAM application. Omega CSP has a newly developed dielectric polymer as a stress buffer and modified redistribution process. This work aimed at the assessment of the solder joint reliability characteristics and the runner metal reliability. We studied and examined the reliability in terms of the property of dielectric polymer and the runner structure. According to the results, it was found that solder joint reliability strongly depended on the solder ball size and runner thickness. In addition, the effects of CTE/modulus of dielectric polymer on the reliability solder joint will be discussed.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125150534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Influence of chemistry and applied stress on reliability of polymer and substrate interfaces 化学和外加应力对聚合物和衬底界面可靠性的影响
S. Leung, S. Luo, D. Lam, C. Wong
{"title":"Influence of chemistry and applied stress on reliability of polymer and substrate interfaces","authors":"S. Leung, S. Luo, D. Lam, C. Wong","doi":"10.1109/ECTC.2000.853217","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853217","url":null,"abstract":"Epoxy-based underfills in flip-chip assembly have been widely employed to enhance electronic package reliability. Addition of coupling agent in the underfill encapsulant can increase the adhesive bonding by introducing chemical bonding across the interface. The stability of this interfacial bonding is depended on the active chemicals and residual stress from curing and thermal mismatch present at the interface. The effects of chemicals and stresses have been independently observed to accelerate debonding. A model of the combined influence of stress and chemistry on the debonding rate has been proposed, but data on the combined influence of chemical and stress are not available. In this study, the stress-assisted interfacial debonding of epoxy adhesives is quantified. Underfill adhesives with silane coupling agent, titanate coupling agent, and zirconate coupling agent were characterized. Basic material properties including the curing behavior, coefficient of thermal expansion, glass transition temperature, elastic modulus and moisture absorption profile were measured by differential scanning calorimetry, thermal mechanical analysis, 3-point bending test and dynamic mechanical analysis. Debonding rates of adhesives under varied applied stress conditions were characterized using tapered double cantilever beam specimens. The implications of the data and the kinetic parameters on material choices are discussed with respect to electronic packaging reliability.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126499777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
800 Mbit/s/ch/spl times/12 ch, true DC-coupled parallel optical interconnects using single-mode fiber and 1310 nm LD array 800mbit /s/ch/spl times/ 12ch,使用单模光纤和1310nm LD阵列实现真正的dc耦合并行光互连
A. Takai, H. Furuichi, A. Miura, K. Tonehira, K. Kawamoto, S. Ueno, Y. Fukashiro, T. Haga, T. Toyonaka, K. Yamada, T. Suejima, K. Saitoh
{"title":"800 Mbit/s/ch/spl times/12 ch, true DC-coupled parallel optical interconnects using single-mode fiber and 1310 nm LD array","authors":"A. Takai, H. Furuichi, A. Miura, K. Tonehira, K. Kawamoto, S. Ueno, Y. Fukashiro, T. Haga, T. Toyonaka, K. Yamada, T. Suejima, K. Saitoh","doi":"10.1109/ECTC.2000.853202","DOIUrl":"https://doi.org/10.1109/ECTC.2000.853202","url":null,"abstract":"We developed 800 Mbit/s/ch, 12 ch, DC-coupled parallel optical interconnect modules, and confirmed high speed parallel transmission. For skew reduction between channels, we use single mode fiber array. In transmitter module, laser turn-on delay time is reduced by edge-pulse modulation method. In receiver module, 4 GHz-bandwidth receiver IC enables one to suppress waveform distortion caused by optical power variation. For assemblability and reliability, planar micro lens arrays are used for optical coupling and hermetic sealing.","PeriodicalId":410140,"journal":{"name":"2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125771885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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