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Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)最新文献

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High-performance clocking and digital synthesis - Session 8 高性能时钟和数字合成-会话8
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358756
J. D. V. Tang
{"title":"High-performance clocking and digital synthesis - Session 8","authors":"J. D. V. Tang","doi":"10.1109/cicc.2004.1358756","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358756","url":null,"abstract":"High performance digital systems require precise clock signals that have accurate phase position and low timing jitter or phase noise. As digital systems improve with each process generation and the applications addressed expand, the performance requirements of the clocking circuits become evermore stringent and varied, while the economics of the chip business, require attention during design to block reuse. This session presents an interesting array of clocking circuits from Phase Lock Loops (PLL), Delay Lock Loops (DLL), Clock & Data Recovery (CDR) blocks to Direct Digital Synthesizers (DDS).","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integrated oscillators and tuning elements - Session 13 集成振荡器和调谐元件-会话13
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358791
E. Charbon, R. Gharpurey
{"title":"Integrated oscillators and tuning elements - Session 13","authors":"E. Charbon, R. Gharpurey","doi":"10.1109/cicc.2004.1358791","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358791","url":null,"abstract":"The papers in this session address design and process techniques for efficient implementation of integrated oscillators and passive elements. The quality of oscillators and filters plays a major role in determining the dynamic range and selectivity of wireless transceivers. The performance of these circuits is in turn strongly dependent on the quality of passives available in the process technology that is used for implementation.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131636205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interconnect and noise modeling - Session 24 互连和噪声建模-第24节
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358860
{"title":"Interconnect and noise modeling - Session 24","authors":"","doi":"10.1109/cicc.2004.1358860","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358860","url":null,"abstract":"As semiconductor technologies continue to scale down, new challenges have surfaced in the areas of timing closure and noise coupling. As technologies continue to push the metal spacings to fulfill the insatiable appetite for increased chip density, the interconnects themselves have become performance limitators due to attenuation, crosstalk, and dispersion. At the same time, market requirements are driving chip designers to combine noisesensitive analog circuits with high-speed, noise-generating digital circuits. The papers in this session address these problems by presenting inductance and capacitance extraction methods, interconnect modeling, noise coupling, and dynamic power integrity analysis.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130547941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Signal and data processors - Session 27 信号和数据处理器。第27节
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358887
R. Krishnamurthy, L. Clark
{"title":"Signal and data processors - Session 27","authors":"R. Krishnamurthy, L. Clark","doi":"10.1109/cicc.2004.1358887","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358887","url":null,"abstract":"Signal and data processing encompasses a wide range of applications, from image recognition to ultra-wideband communications systems. Digital signal processors are enabling embedded components in consumer electronics, cellular communications, and other hand-held devices, where power is as important as performance. The session begins with papers describing multithreaded processors, including design for low power. The session moves on to signal processing papers and concludes with two presentations describing reconfigurable data processing integrated circuits.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122219526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Custom circuits for interfaces and imaging - Session 14 接口和成像的自定义电路。会话14
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358798
T. Kuroda, T. Sakurai
{"title":"Custom circuits for interfaces and imaging - Session 14","authors":"T. Kuroda, T. Sakurai","doi":"10.1109/cicc.2004.1358798","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358798","url":null,"abstract":"The first paper of the session is discussing an area-efficient system LSI used for DVD products. A 0.13-pm CMOS is employed. By optimizing the chip architecture and implementation scheme, the SoC successfully reduced the die size from previous 64 mm2 to this 34 mm2 without degrading the performance and functionality. Fully digital equalizers with oversampling method is employed in the novel PRML (Partial Response Maximum Likelihood) read channel to improve system stability while maintaining channel quality.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122465367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-speed serical links - Session 3 高速业务链路。会话3
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358722
J. Savoj, Kumar Lakshimikumar
{"title":"High-speed serical links - Session 3","authors":"J. Savoj, Kumar Lakshimikumar","doi":"10.1109/cicc.2004.1358722","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358722","url":null,"abstract":"Advancements in semiconductor technologies have enabled transceiver circuits operating at very high data rates. However, these devices often have to work with legacy transmission media which are plagued by limitations such as low bandwidth and high levels of crosstalk. This calls for the use of signal processing techniques to provide robust communication. This session highlights several equalization techniques and a signaling approach that enable very high-speed serial data communication.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"500 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116548234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analoa technigues - Session 29
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358905
D. Nairn
{"title":"Analoa technigues - Session 29","authors":"D. Nairn","doi":"10.1109/cicc.2004.1358905","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358905","url":null,"abstract":"To achieve accuracy, stable references and well matched circuits are typically required. In the fust paper, techniques for designing bandgap reference voltages that operate with low-voltage supplies are explored and many different approaches are illustrated. In the second paper, the trade-off between device matching and die area is explored with the goal of simultaneously minimizing the device mismatches and die area of a bandgap reference. An alternate approach to implementing a reference is to trim the circuit after fabrication. The use of trimmable floating gates is used in the third paper to implement a temperature, process and supply independent reference voltage.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130541505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Prop-rammable architectures - Session 19 可编程架构-第19部分
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358837
J. Wright
{"title":"Prop-rammable architectures - Session 19","authors":"J. Wright","doi":"10.1109/cicc.2004.1358837","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358837","url":null,"abstract":"Structured ASICs consist of a regular array of pre-designed logic elements that can be interconnected as needed to implement a user's circuit. The \"programming\" of these devices involves fabricating a small number of metal mask or via layers in a silicon foundry. Since most of the mask layers on the chip are the same for all designs, with only the final metal or via layers being customized for a particular circuit, manufacturing time, and risk, is decreased compared to traditional standard cell ASICs. Our first three papers examine design issues for structured ASICs.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"30 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115969782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Introduction to silicon debug and SoC test - Session 30 介绍硅调试和SoC测试-第30节
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358913
McGiII Universi
{"title":"Introduction to silicon debug and SoC test - Session 30","authors":"McGiII Universi","doi":"10.1109/cicc.2004.1358913","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358913","url":null,"abstract":"","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121065915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SoC solutions for nanometer desian - Session 15 纳米设计的SoC解决方案-第15期
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358806
Ricki Williams
{"title":"SoC solutions for nanometer desian - Session 15","authors":"Ricki Williams","doi":"10.1109/cicc.2004.1358806","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358806","url":null,"abstract":"Present day semiconductor process advances are enabling the proliferation and successful realization of complete systems-on-a-chip. Integrating processors, memory, specialized embedded logic, along side analog and even RF circuits on a single die is becoming extremely challenging. Managing these complexities while optimizing the tradeoffs between hardware and software, cost, as well as time to market, calls for new strategies, disciplines, and innovative design methodologies.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125257058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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