High-performance clocking and digital synthesis - Session 8

Abstract

High performance digital systems require precise clock signals that have accurate phase position and low timing jitter or phase noise. As digital systems improve with each process generation and the applications addressed expand, the performance requirements of the clocking circuits become evermore stringent and varied, while the economics of the chip business, require attention during design to block reuse. This session presents an interesting array of clocking circuits from Phase Lock Loops (PLL), Delay Lock Loops (DLL), Clock & Data Recovery (CDR) blocks to Direct Digital Synthesizers (DDS).