{"title":"A breakdown voltage doubler for high voltage swing drivers","authors":"Sam Mandegaran, A. Hajimiri","doi":"10.1109/CICC.2004.1358747","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358747","url":null,"abstract":"A novel breakdown voltage (BV) doubler is introduced that makes it possible to generate high output voltage swings using transistors with low breakdown voltages. The timing analysis of the stage is used to optimize its dynamic response. A 10 Gb/s optical modulator driver with a differential output voltage swing of 8 V on a 50 /spl Omega/ load was implemented in a SiGe BiCMOS process. It uses the BV-doubler topology to achieve output swings twice the collector-emitter breakdown voltage without stressing any single transistor.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114651409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sergey V. Rylov, S. Reynolds, D. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, M. Sorna
{"title":"10+ Gb/s 90nm CMOS serial link demo in CBGA package","authors":"Sergey V. Rylov, S. Reynolds, D. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, M. Sorna","doi":"10.1109/CICC.2004.1358725","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358725","url":null,"abstract":"We report a 10+ Gb/s serial link demo chip in 90-nm CMOS. It consists of a full-rate 4:1 MUX with 8-tap feed-forward equalizer, a half-rate 1:4 DEMUX with programmable peaking pre-amplifier, and a parallel port interface. The chip is housed in CBGA package and uses ESD devices on all pins. The measured maximum speed of stand-alone transmitter and receiver was 11.7 Gb/s and 13.3 Gb/s respectively, and maximum back-to-back operation speed (transmitter+receiver) was 11.4 Gb/s.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116988750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Ku-band monolithic tuner-LNB for satellite applications [low noise block down-converter]","authors":"G. Girlando, T. Copani, S. Smerzi, G. Palmisano","doi":"10.1109/CICC.2004.1358900","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358900","url":null,"abstract":"A 12-GHz monolithic tuner for digital video broadcasting via satellite (DVB-S) applications is presented. The tuner is able to convert the typical 36-MHz wide DVB-S channel, lying in the Ku-band (10.7-12.75 GHz), to a fixed 1.45 GHz intermediate frequency (IF). The IC consists of a down-converter block and a PLL that implements a programmable divider. When the LO frequency is set between 9.25 and 11.3 GHz, the phase noise is lower than -115 dBc/Hz at 1-MHz offset. For an 11.7-GHz input signal, the conversion gain is 34.5 dB, the single-sideband noise figure is as low as 7.5 dB, while the 1-dB output compression point is as high as +5 dBm. Over the entire RF band, the conversion gain variation is within 3 dB. This first Ku-band monolithic tuner represents an improvement compared to the traditional low noise block down-converter (LNB). Indeed, instead of down-converting a wide RF band, the tuner-LNB directly selects the desired DVB-S channel. Thus, a more flexible use of the antenna cable bandwidth is achieved.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123604723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Process variation in nano-scale memories: failure analysis and process tolerant architecture","authors":"A. Agarwal, B. Paul, K. Roy","doi":"10.1109/CICC.2004.1358819","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358819","url":null,"abstract":"In this paper, we analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process tolerant cache architecture suitable for high performance memory. This technique surpasses all the contemporary fault tolerant schemes such as row/column redundancy and ECC in handling failures due to process variation. Experimental results on a 64K cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in 45nm predictive technology.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121150855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Peter Bode, A. Lampe, M. Helfenstein, Michael Gollnick
{"title":"Improved method for measuring frequency ratios in GSM mobile phones","authors":"Peter Bode, A. Lampe, M. Helfenstein, Michael Gollnick","doi":"10.1109/CICC.2004.1358902","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358902","url":null,"abstract":"The principle of operation of the ubiquitous low-cost digital circuits for frequency measurement appears to have remained unchanged for decades. In applications with very high accuracy requirements, such as in GSM mobile phones, these conventional solutions can lead to excessive measurement periods with detrimental effect on the stand-by time. In this paper, we present a novel frequency measurement technique which is based on regression algorithms. Experiments with a hardware implementation prove that the crucial product of measurement error and measurement period can be reduced by orders of magnitude compared to conventional solutions while the slight extension of the digital circuitry is virtually for free.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121178353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]","authors":"A. Maxim","doi":"10.1109/CICC.2004.1358760","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358760","url":null,"abstract":"A low-noise ring oscillator based PLL frequency synthesizer was realized for wideband tuner applications. The reference spurs are minimized using a fast reset, precharged phase-frequency-detector and a dynamic current matching charge-pump. The PLL has a single power supply, while a shunt regulator was used to bias the digital blocks without coupling noise to the analog supply. A two stage symmetric NFET load ring oscillator was used for both low phase noise and high frequency operation. A noise attenuating loop filter was implemented, that in conjunction with a Miller capacitance multiplication allows the on-chip integration of the loop filter capacitor.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114844213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Crosstalk coupling effects of CMOS co-planar spiral inductors","authors":"J. Mikkelsen, O. K. Jensen, T. Larsen","doi":"10.1109/CICC.2004.1358825","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358825","url":null,"abstract":"The coupling effects between two adjacent co-planar spiral inductors are characterized in two cases, one where no guard structure is used and one where simple guard-rings are used. In addition, the effect of guard-rings is evaluated at different distances (190 /spl mu/m to 1090 /spl mu/m) between inductors. The model traditionally used to predict this crosstalk is found to be insufficient and an extended model including mutual inductive coupling and direct capacitive coupling is shown to provide accurate fit. Measuring low levels of crosstalk is difficult and in this context the effect of the test fixture itself is evaluated. Return current paths are here found to have significant influence on low frequency results. Also, based on laser cutting of test fixtures, a surrounding ground-ring is found to increase the crosstalk level. The use of simple guard-rings is shown to improve isolation by approximately 10-15 dB for closely spaced adjacent inductors. At larger distances the gain from having a guard-ring reduces and eventually reduces to zero at a distance of 1000 /spl mu/m. For closely spaced devices a doubling of distance is found to provide an additional 20 dB attenuation of crosstalk.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123092774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Mergens, J. Armer, P. Jozwiak, B. Keppens, Frederic De Ranter, K. Verhaege, R. Kumar
{"title":"Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies","authors":"M. Mergens, J. Armer, P. Jozwiak, B. Keppens, Frederic De Ranter, K. Verhaege, R. Kumar","doi":"10.1109/CICC.2004.1358790","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358790","url":null,"abstract":"This paper presents a novel active-source-pump (ASP) circuit technique to significantly lower the ESD sensitivity of ultrathin gate inputs in advanced sub-90nm CMOS technologies. As demonstrated by detailed experimental analysis, an ESD design window expansion of more than 100% can be achieved. This revives conventional ESD solutions for ultrasensitive input protection also enabling low-capacitance RF protection schemes with a high ESD design flexibility at IC-level. ASP IC application examples, and the impact of ASP on normal RF operation performance, are discussed.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiple integration method for high signal-to-noise ratio readout integrated circuit [IR focal plane array applications]","authors":"S. Kang, D. Woo, Hee-Chul Lee","doi":"10.1109/CICC.2004.1358804","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358804","url":null,"abstract":"This paper reports a multiple integration method for providing a greatly improved signal-to-noise ratio for high resolution infrared focal plane array (FPA) applications. In this method, the signal from each pixel is repeatedly sampled into the integration capacitor, and then outputted and summed into outside memory, continuing for n read cycles during the period of a frame, so that the effective charge integration capacity is increased and the sensitivity is improved. It requires a low noise function block and high speed operation of the readout circuit, so a new concept of readout circuit, performing digitization by the voltage skimming method, is proposed. The readout circuit has been fabricated using a 0.6 /spl mu/m CMOS process for a 64/spl times/64 mid-wavelength infrared (MWIR) HgCdTe detector array. It has been found that the readout circuit can effectively increase the charge storage capacity up to 2.4/spl times/10/sup 8/ electrons, and then provides a greatly improved signal-to-noise ratio by approximately a factor of 3.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122739832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jim Brown, Reed Packer, Jagdish Prasad, Khris Kofford, T. Dye, Bob Kirk
{"title":"Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay","authors":"Jim Brown, Reed Packer, Jagdish Prasad, Khris Kofford, T. Dye, Bob Kirk","doi":"10.1109/CICC.2004.1358841","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358841","url":null,"abstract":"System designers face an ever more complex set of tradeoffs in developing advanced digital systems. Transistors are getting faster, interconnect is getting slower, signal integrity issues are getting more complex, and reticle costs are exploding at an exponential rate. This paper takes a look at a unique hybrid processing approach for structured ASICs which reduces reticle costs and avoids many of the interconnect issues associated with ultra-deep sub-micron (UDSM) processes. In particular it investigates the impact of reduced programmable interconnect levels on routing congestion and performance relative to comparable cell-based ASIC technologies. Two designs are used to compare structured ASICs to a 180nm standard cell technology. The comparison metrics include maximum clock rate, density, area, clock latency, clock skew and CT fan out.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130100265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}