发布求助
文献互助 智能选刊 最新文献

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)最新文献

筛选
英文 中文
Differential transmission line interconnect for high speed and low power global wiring 差动传输线互连用于高速和低功率的全球布线
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI: 10.1109/CICC.2004.1358811
S. Gomi, Kohichi Nakamura, Hiroyuki Ito, K. Okada, K. Masu
{"title":"Differential transmission line interconnect for high speed and low power global wiring","authors":"S. Gomi, Kohichi Nakamura, Hiroyuki Ito, K. Okada, K. Masu","doi":"10.1109/CICC.2004.1358811","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358811","url":null,"abstract":"This paper proposes transmission line interconnect, which achieves high speed and low power consumption for global interconnects. The delay time and power consumption are evaluated at 4 Gbps signal frequency. RLC differential transmission line is faster than RC line when interconnect length is over 2.4 mm. RLC line has lower power consumption than RC line over 7.0 mm. Increasing interconnect area can be suppressed by using the diagonal-pair line structure as the differential transmission line.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117345599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 5-GHz silicon bipolar transmitter front-end for wireless LAN applications 用于无线局域网应用的5 ghz硅双极发射机前端
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI: 10.1109/CICC.2004.1358882
A. Italia, L. Paglia, A. Scuderi, F. Carrara, E. Ragonese, G. Palmisano
{"title":"A 5-GHz silicon bipolar transmitter front-end for wireless LAN applications","authors":"A. Italia, L. Paglia, A. Scuderi, F. Carrara, E. Ragonese, G. Palmisano","doi":"10.1109/CICC.2004.1358882","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358882","url":null,"abstract":"A 5-GHz transmitter front-end for IEEE 802.11a and HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-f/sub T/ silicon bipolar technology. The transmitter includes a digitally controlled linear-in-dB variable-gain up-converter and a three-stage linear power amplifier. At a 3-V supply voltage, the front-end exhibits a 23.5-dBm output 1-dB compression point, 35-dB maximum power gain, and 30-dB dynamic range. The dB-linear gain error is lower than /spl plusmn/0.8 dB. The transmitter is able to comply with the stringent error vector magnitude requirement of the standard up to a 19-dBm output power level.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123375835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A programmable floating-gate voltage reference in 0.5 /spl mu/m CMOS 0.5 /spl mu/m CMOS的可编程浮栅基准电压
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI: 10.1109/CICC.2004.1358909
Seth A. Cook, K. Layton, W. J. Marble, D. Comer, D. Comer, C. Petrie
{"title":"A programmable floating-gate voltage reference in 0.5 /spl mu/m CMOS","authors":"Seth A. Cook, K. Layton, W. J. Marble, D. Comer, D. Comer, C. Petrie","doi":"10.1109/CICC.2004.1358909","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358909","url":null,"abstract":"A floating-gate voltage reference (FGVREF) circuit is presented in which novel implementations of a transconductance amplifier and a transimpedance amplifier are combined to isolate the floating gate from the variations in temperature and power supply that adversely affect most FGVREF circuits. This FGVREF circuit uses this isolation to improve the power supply rejection ratio to greater than 80 dB and temperature coefficient to 54.6 ppm//spl deg/C while maintaining the size, programmability, and CMOS compatibility advantages as compared to typical bandgap references. The programmable FGVREF, which operates from a 2.8 V to 5.5 V supply, dissipates 100 /spl mu/A from a 5 V supply and occupies an area of less than 0.011 mm/sup 2/ in a 0.5 /spl mu/m CMOS process.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127827665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface 一种90 nm FPGA I/O缓冲设计，源同步系统数据速率为1.6 Gbps，外部存储器接口时钟速率为300 MHz
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI: 10.1109/CICC.2004.1358843
Jeffrey Tyhach, Bonnie Wang, C. Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Y. Chong, P. Pan, Henry Kim, Gopinath Rangan, T. Chang, Johnson Tan
{"title":"A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface","authors":"Jeffrey Tyhach, Bonnie Wang, C. Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Y. Chong, P. Pan, Henry Kim, Gopinath Rangan, T. Chang, Johnson Tan","doi":"10.1109/CICC.2004.1358843","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358843","url":null,"abstract":"As FPGAs become more integrated into high-speed systems, high performance I/O with excellent signal integrity becomes more important. This paper describes how these challenges were met on an FPGA developed to support 1.6 Gbps differential source-synchronous standards and 300 MHz external memory interfaces. The I/O buffer features programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3v tolerance. High-speed performance was achieved using design techniques of differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. In addition, DLLs and programmable phase offset circuits were used to obtain precise timing control. The chip was manufactured on a 90 nm CMOS process.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122767348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
GSM DAC with new segmented mismatch shaping technique 采用新的分段失配整形技术的GSM DAC
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI: 10.1109/CICC.2004.1358772
A. Shabra, J. Gealow, P. Ferguson
{"title":"GSM DAC with new segmented mismatch shaping technique","authors":"A. Shabra, J. Gealow, P. Ferguson","doi":"10.1109/CICC.2004.1358772","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358772","url":null,"abstract":"An area-efficient 10-bit 6.5 Msps digital to analog converter (DAC), for the transmit and power ramping DACs of a GSM mixed signal solution, is presented. Using a segmented mismatch shaping approach, the design simultaneously offers the signal to noise ratio needed to achieve good modulation accuracy, and the low out-of-band noise needed to satisfy transmit emissions requirements specified in the GSM standard.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132294788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement and modeling of noise parameters for desensitized low noise amplifiers 脱敏低噪声放大器噪声参数的测量与建模
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI: 10.1109/CICC.2004.1358829
Gaurab Banerjee, D. Becher, C. Hung, D. Allstot, K. Soumyanath
{"title":"Measurement and modeling of noise parameters for desensitized low noise amplifiers","authors":"Gaurab Banerjee, D. Becher, C. Hung, D. Allstot, K. Soumyanath","doi":"10.1109/CICC.2004.1358829","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358829","url":null,"abstract":"It can be shown that devices with low noise resistance (R/sub n/) values can significantly relax the noise-input match trade-off in LNA design, resulting in desensitized wideband LNAs. In this paper, we show that the measurements of such devices are error-prone and can cause modeling and simulation inaccuracies. Using a CAD-oriented approach, an error-propagation analysis from measurements to a device-model is performed. We find that the errors in measurements affect the simulated values of R/sub n/, NF/sub min/ and B/sub opt/ the least and these parameters need to be calibrated well in any good device model. Values of G/sub opt/ are shown to propagate from measurements and errors are bigger for devices with a large transadmittance (/sub y21/). We suggest the use of scaled MOS models extracted from devices with high R/sub n/ to predict the values of G/sub opt/ for devices with low R/sub n/, using the other noise parameters as calibration points.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132116127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes 基于电荷收集和寄生双极失效模式的SRAM中子诱导误差分析
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI: 10.1109/CICC.2004.1358820
K. Osada, N. Kitai, S. Kamohara, T. Kawahara
{"title":"Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes","authors":"K. Osada, N. Kitai, S. Kamohara, T. Kawahara","doi":"10.1109/CICC.2004.1358820","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358820","url":null,"abstract":"This paper describes an investigation of the upsetting of values in cells hit by alpha particles or neutrons, in which the feedback operation of the cross-coupled inverter in SRAM is accurately modeled through simultaneous device and circuit simulation. We demonstrate, for the first time, the existence and mechanism of a new parasitic-bipolar-failure (PBF) mode. Accurate values of critical charge (Q/sub cg/) for failure are calculated for both this mode and the conventional charge-collection-failure (CCF) mode. We identify opposite behaviors of Q/sub cg/ for the CCF and PBF modes with respect to the amount of charge at the storage node (Q/sub node/). The results on critical charge are also used to predict the soft-error rate and the prediction agrees with the results of measurement to within 30%. Based on the results, we propose design techniques for reduced SER.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116173507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS 3D camera with millimetric depth resolution 具有毫米深度分辨率的CMOS 3D相机
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI: 10.1109/CICC.2004.1358925
C. Niclass, A. Rochas, P. Besse, E. Charbon
{"title":"A CMOS 3D camera with millimetric depth resolution","authors":"C. Niclass, A. Rochas, P. Besse, E. Charbon","doi":"10.1109/CICC.2004.1358925","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358925","url":null,"abstract":"A 3D imager is presented, capable of capturing the depth map of an arbitrary scene. Depth is measured by computing the time-of-flight of a ray of light as it leaves the source and is reflected by the objects in the scene. The round-trip time is converted to a digital code independently for each pixel using a CMOS time-to-digital converter. To reach millimetric accuracies an array of 32/spl times/32 highly sensitive, ultra-low jitter CMOS detectors capable of detecting a single photon is used. The scene is illuminated using a cone of low power pulsed laser light, thus no mechanical scanning devices or expensive optical equipment are required.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116865598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Specialized custom circuits - Session 6 专门定制电路-第6节
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/cicc.2004.1358741
J. Snyder
{"title":"Specialized custom circuits - Session 6","authors":"J. Snyder","doi":"10.1109/cicc.2004.1358741","DOIUrl":"https://doi.org/10.1109/cicc.2004.1358741","url":null,"abstract":"Deep sub-micron technologies dictated circuit design techniques that emphasized power management through clock gating, dynamic voltage scaling, sleep mode(s), and device sizing; to mention but a few of those techniques. It also enabled a high level of integration which dictated managing several clock domains on a single chip. Meanwhile, noise, signal integrity, and low device breakdown voltages continue to make circuit design more challenging.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122919553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond 一种用于90纳米及以上SoC的软误差硬化锁存器方案
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI: 10.1109/CICC.2004.1358812
Y. Komatsu, Y. Arima, T. Fujimoto, T. Yamashita, K. Ishibashi
{"title":"A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond","authors":"Y. Komatsu, Y. Arima, T. Fujimoto, T. Yamashita, K. Ishibashi","doi":"10.1109/CICC.2004.1358812","DOIUrl":"https://doi.org/10.1109/CICC.2004.1358812","url":null,"abstract":"In this paper, we proposed a soft-error hardened latch (SEH-latch) scheme that has an error correction function in the fine process. To achieve this, we designed two types of SEH-latch circuits and a standard latch circuit using 130 nm 2-well, and also 90 nm 2-well CMOS processes. The proposed circuit demonstrated 2-order higher immunity through a radiation test using /spl alpha/-particles, and 1-order higher immunity through neutron irradiation.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122048910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信