0.5 /spl mu/m CMOS的可编程浮栅基准电压

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 2004-11-22 DOI:10.1109/CICC.2004.1358909

Seth A. Cook, K. Layton, W. J. Marble, D. Comer, D. Comer, C. Petrie

{"title":"0.5 /spl mu/m CMOS的可编程浮栅基准电压","authors":"Seth A. Cook, K. Layton, W. J. Marble, D. Comer, D. Comer, C. Petrie","doi":"10.1109/CICC.2004.1358909","DOIUrl":null,"url":null,"abstract":"A floating-gate voltage reference (FGVREF) circuit is presented in which novel implementations of a transconductance amplifier and a transimpedance amplifier are combined to isolate the floating gate from the variations in temperature and power supply that adversely affect most FGVREF circuits. This FGVREF circuit uses this isolation to improve the power supply rejection ratio to greater than 80 dB and temperature coefficient to 54.6 ppm//spl deg/C while maintaining the size, programmability, and CMOS compatibility advantages as compared to typical bandgap references. The programmable FGVREF, which operates from a 2.8 V to 5.5 V supply, dissipates 100 /spl mu/A from a 5 V supply and occupies an area of less than 0.011 mm/sup 2/ in a 0.5 /spl mu/m CMOS process.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A programmable floating-gate voltage reference in 0.5 /spl mu/m CMOS\",\"authors\":\"Seth A. Cook, K. Layton, W. J. Marble, D. Comer, D. Comer, C. Petrie\",\"doi\":\"10.1109/CICC.2004.1358909\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A floating-gate voltage reference (FGVREF) circuit is presented in which novel implementations of a transconductance amplifier and a transimpedance amplifier are combined to isolate the floating gate from the variations in temperature and power supply that adversely affect most FGVREF circuits. This FGVREF circuit uses this isolation to improve the power supply rejection ratio to greater than 80 dB and temperature coefficient to 54.6 ppm//spl deg/C while maintaining the size, programmability, and CMOS compatibility advantages as compared to typical bandgap references. The programmable FGVREF, which operates from a 2.8 V to 5.5 V supply, dissipates 100 /spl mu/A from a 5 V supply and occupies an area of less than 0.011 mm/sup 2/ in a 0.5 /spl mu/m CMOS process.\",\"PeriodicalId\":407909,\"journal\":{\"name\":\"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2004.1358909\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2004.1358909","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

提出了一种浮门基准电压(FGVREF)电路，其中跨导放大器和跨阻放大器的新实现相结合，以隔离浮门不受温度和电源变化的影响，这些变化对大多数FGVREF电路产生不利影响。FGVREF电路利用这种隔离将电源抑制比提高到80 dB以上，温度系数提高到54.6 ppm//spl度/C，同时与典型带隙参考器件相比，保持尺寸、可编程性和CMOS兼容性优势。可编程FGVREF的工作电压为2.8 V至5.5 V，功耗为100 /spl mu/ a，在0.5 /spl mu/m CMOS工艺中占地面积小于0.011 mm/sup 2/。

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A programmable floating-gate voltage reference in 0.5 /spl mu/m CMOS

A floating-gate voltage reference (FGVREF) circuit is presented in which novel implementations of a transconductance amplifier and a transimpedance amplifier are combined to isolate the floating gate from the variations in temperature and power supply that adversely affect most FGVREF circuits. This FGVREF circuit uses this isolation to improve the power supply rejection ratio to greater than 80 dB and temperature coefficient to 54.6 ppm//spl deg/C while maintaining the size, programmability, and CMOS compatibility advantages as compared to typical bandgap references. The programmable FGVREF, which operates from a 2.8 V to 5.5 V supply, dissipates 100 /spl mu/A from a 5 V supply and occupies an area of less than 0.011 mm/sup 2/ in a 0.5 /spl mu/m CMOS process.

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Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

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