A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Pub Date : 1900-01-01 DOI:10.1109/CICC.2004.1358812

Y. Komatsu, Y. Arima, T. Fujimoto, T. Yamashita, K. Ishibashi

引用次数: 36

Abstract

In this paper, we proposed a soft-error hardened latch (SEH-latch) scheme that has an error correction function in the fine process. To achieve this, we designed two types of SEH-latch circuits and a standard latch circuit using 130 nm 2-well, and also 90 nm 2-well CMOS processes. The proposed circuit demonstrated 2-order higher immunity through a radiation test using /spl alpha/-particles, and 1-order higher immunity through neutron irradiation.

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一种用于90纳米及以上SoC的软误差硬化锁存器方案

本文提出了一种在精细加工过程中具有误差校正功能的软误差硬化锁存器(sei -latch)方案。为了实现这一目标，我们设计了两种类型的seh锁存电路和一个标准锁存电路，使用130 nm 2-well和90 nm 2-well CMOS工艺。通过使用/spl α /-粒子的辐射测试，该电路的抗扰度提高了2级;通过中子辐照，该电路的抗扰度提高了1级。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

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