Process variation in nano-scale memories: failure analysis and process tolerant architecture

Abstract

In this paper, we analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process tolerant cache architecture suitable for high performance memory. This technique surpasses all the contemporary fault tolerant schemes such as row/column redundancy and ECC in handling failures due to process variation. Experimental results on a 64K cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in 45nm predictive technology.