Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]

A low-noise ring oscillator based PLL frequency synthesizer was realized for wideband tuner applications. The reference spurs are minimized using a fast reset, precharged phase-frequency-detector and a dynamic current matching charge-pump. The PLL has a single power supply, while a shunt regulator was used to bias the digital blocks without coupling noise to the analog supply. A two stage symmetric NFET load ring oscillator was used for both low phase noise and high frequency operation. A noise attenuating loop filter was implemented, that in conjunction with a Miller capacitance multiplication allows the on-chip integration of the loop filter capacitor.