Interconnect and noise modeling - Session 24

Abstract

As semiconductor technologies continue to scale down, new challenges have surfaced in the areas of timing closure and noise coupling. As technologies continue to push the metal spacings to fulfill the insatiable appetite for increased chip density, the interconnects themselves have become performance limitators due to attenuation, crosstalk, and dispersion. At the same time, market requirements are driving chip designers to combine noisesensitive analog circuits with high-speed, noise-generating digital circuits. The papers in this session address these problems by presenting inductance and capacitance extraction methods, interconnect modeling, noise coupling, and dynamic power integrity analysis.