{"title":"Prop-rammable architectures - Session 19","authors":"J. Wright","doi":"10.1109/cicc.2004.1358837","DOIUrl":null,"url":null,"abstract":"Structured ASICs consist of a regular array of pre-designed logic elements that can be interconnected as needed to implement a user's circuit. The \"programming\" of these devices involves fabricating a small number of metal mask or via layers in a silicon foundry. Since most of the mask layers on the chip are the same for all designs, with only the final metal or via layers being customized for a particular circuit, manufacturing time, and risk, is decreased compared to traditional standard cell ASICs. Our first three papers examine design issues for structured ASICs.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"30 24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/cicc.2004.1358837","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Structured ASICs consist of a regular array of pre-designed logic elements that can be interconnected as needed to implement a user's circuit. The "programming" of these devices involves fabricating a small number of metal mask or via layers in a silicon foundry. Since most of the mask layers on the chip are the same for all designs, with only the final metal or via layers being customized for a particular circuit, manufacturing time, and risk, is decreased compared to traditional standard cell ASICs. Our first three papers examine design issues for structured ASICs.