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Corporate Partnerships Establish an Asynchronous Learning Initiative with the University of the Philippines, College of Engineering 与菲律宾大学工程学院建立异步学习计划
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638784
M. Saquilayan, J. Tulao, M. Benitez, T. Hall, R. Jensen, N. S. Que
{"title":"Corporate Partnerships Establish an Asynchronous Learning Initiative with the University of the Philippines, College of Engineering","authors":"M. Saquilayan, J. Tulao, M. Benitez, T. Hall, R. Jensen, N. S. Que","doi":"10.1109/ASMC.2006.1638784","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638784","url":null,"abstract":"In this paper, we describe the corporate/university partnership to address critical business challenges by leveraging the content and resources available through a university and using a delivery methodology of asynchronous distance learning","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133526850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Evaluation of Serial Photolithography Clusters: Queueing Models, Throughput and Workload Sequencing 串行光刻簇的性能评估:排队模型，吞吐量和工作负载排序
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638722
J. R. Morrison, B. Bortnick, D.P. Martin
{"title":"Performance Evaluation of Serial Photolithography Clusters: Queueing Models, Throughput and Workload Sequencing","authors":"J. R. Morrison, B. Bortnick, D.P. Martin","doi":"10.1109/ASMC.2006.1638722","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638722","url":null,"abstract":"For clustered configuration of a photolithography toolset, operating under a scheduling policy inducing serial processing, measures of system performance are deduced. Queueing models demonstrate that, due to the parallelism inherent in the system configuration, the normalized cycle time behavior is different than that of the standard single server queue. Cluster throughput is evaluated based on measures of the frequency and magnitude of events common in manufacturing operation. It is shown that the maximum throughput of a serial photolithography cluster tool is not influenced by the order in which two classes of lots with different wafer processing speeds are processed","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132258445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Enabling Facility Re-Use for 300mm Semiconductor Manufacturing via Integration of Automated Material Handling System and Facility Design 通过集成自动化物料处理系统和设备设计，实现300mm半导体制造的设备再利用
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638764
S. Seall, D. Steele, M. Jung
{"title":"Enabling Facility Re-Use for 300mm Semiconductor Manufacturing via Integration of Automated Material Handling System and Facility Design","authors":"S. Seall, D. Steele, M. Jung","doi":"10.1109/ASMC.2006.1638764","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638764","url":null,"abstract":"This paper describes issues faced by Intel during planning for its first conversion of an existing high volume 200mm semiconductor factory to manufacturing on 300mm wafers. A summary of the constraints and challenges, analysis of alternatives, and description of the adopted solution for modifying AMHS and facility design to allow re-use of an existing 200mm semiconductor fab for manufacturing semiconductors on 300mm wafers is discussed","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132909184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Clean Dicing of Compound Semiconductors Using the Water-Jet Guided Laser Technology 利用水射流激光技术对化合物半导体进行清洁切割
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638759
D. Perrottet, S. Green, B. Richerzhagen
{"title":"Clean Dicing of Compound Semiconductors Using the Water-Jet Guided Laser Technology","authors":"D. Perrottet, S. Green, B. Richerzhagen","doi":"10.1109/ASMC.2006.1638759","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638759","url":null,"abstract":"The water-jet-guided laser is a new technology for micro machining that combines a laser beam into a hair-thin, low-pressure water jet for wafer dicing. In addition to silicon, it can dice compound semiconductors such as GaAs, InP and SiC without damage","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131365352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Simulation Study of Robust Dispatching Algorithm for Mixed VLSl Manufacturing 混合VLSl制造鲁棒调度算法仿真研究
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638754
K. Saito
{"title":"Simulation Study of Robust Dispatching Algorithm for Mixed VLSl Manufacturing","authors":"K. Saito","doi":"10.1109/ASMC.2006.1638754","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638754","url":null,"abstract":"The paper describes a new dispatching algorithm for dynamic allocation of works-in-process (WIP), named pseudo periodical priority dispatching (PID), The algorithm is developed to manage WIP at a processing step in an autonomous distributed manufacturing system. The priority of dispatching is examined when each quantum starts, by considering both the amount WIP in the input buffer of the processing station and the arrival rate of WIP. During the quantum, only one type of WIP is assigned to a particular machine. Performance parameters i.e., adjustment rate, throughput, response time, and tardiness when applying (P3D) are compared with the results of the first come first serve (FCFS) and the shortest processing time (SPT) in simulations assuming Poisson arrival. A fluctuation in arrival rate causes large inventories at the processing station The adjustment rate is the lowest and the availability of machines is the highest with P3D, therefore P3D can quickly dissolve a bottleneck. Both P3D and SPT produced shorter response times than FCFS and hath P3D and FCFS produced shorter tardiness than SPT. The small quantum size helps to shorten the response time in P3D. P3D with the minimized quantum size gives a good estimation when setting the due date. P3D achieves a very far dispatching even though the arrival rate differs by 40 times among works in a product-mix. The author concludes from the above results that P3D has a robust dispatching algorithm tit the case of a broad product-mix","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"53 72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124215168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Early detection of crystal defects in the device process flow by electron beam inspection 电子束检测可早期发现器件工艺流程中的晶体缺陷
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638779
O. Moreau, A. Kang, V. Mantovani, I. Mica, M. Polignano, L. Avaro, C. Pastore, G. Pavia
{"title":"Early detection of crystal defects in the device process flow by electron beam inspection","authors":"O. Moreau, A. Kang, V. Mantovani, I. Mica, M. Polignano, L. Avaro, C. Pastore, G. Pavia","doi":"10.1109/ASMC.2006.1638779","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638779","url":null,"abstract":"In this paper, we describe an inline method to reveal crystal defects in the device fabrication process by voltage contrast detection with an electron beam inspection tool. Suitably designed monitor structures are used to this purpose. The correspondence between bright voltage contrast defects and dislocations connecting the transistor source and drain is demonstrated by selective etching followed by SEM review and by TEM inspection. In addition, it is shown that the voltage contrast defects correlate with the leakage current of the dislocation monitor structures, though some electrically active defects are missed by the electron beam inspection. Possible approaches to improve the capture rate of dislocations and correlation to leakage current are discussed. Finally, the correlation between e beam inspection of dislocation monitor structures and parametric test on a 65nm DR wafer is demonstrated","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122598508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Cycle Time Perspectives for Small Transfer Batch Size 小传输批大小的周期时间透视
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638775
D. Wright, T. Chang
{"title":"Cycle Time Perspectives for Small Transfer Batch Size","authors":"D. Wright, T. Chang","doi":"10.1109/ASMC.2006.1638775","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638775","url":null,"abstract":"This paper discusses advantages and disadvantages of smaller transfer batch size in an automated semiconductor factory. A framework is suggested by which the \"theoretical\" cycle time is determined from the point-of-view of the wafer, not the lot. Using this framework, we then look at the possible application of a \"virtual cluster tool\" by identifying requirements on the process times and transport system. Benefits and risks are then discussed for the approach, using a simple example","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124845733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Application of Back-side Alignment of Thick Layers for the Manufacturing of Advanced Power Devices 厚层背面对准技术在先进功率器件制造中的应用
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638732
Jung Kil Lee, R. Chisholm, M. V. D. van der Heijden, K. Best, P. Berge
{"title":"Application of Back-side Alignment of Thick Layers for the Manufacturing of Advanced Power Devices","authors":"Jung Kil Lee, R. Chisholm, M. V. D. van der Heijden, K. Best, P. Berge","doi":"10.1109/ASMC.2006.1638732","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638732","url":null,"abstract":"Back-side alignment was implemented in the thick layer process flow for the production of advanced power devices. The alignment and overlay performance of the back-side alignment scheme are addressed, as well as the benefits in terms of productivity and cost reduction","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124884733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Method of Manufacturing a Low Defect, Low Stress Pre-metal Dielectric Stack for High Reliability and MEMs Applications 一种用于高可靠性和MEMs应用的低缺陷、低应力金属前介电堆的制造方法
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638729
J. Naughton, M. Nelson
{"title":"A Method of Manufacturing a Low Defect, Low Stress Pre-metal Dielectric Stack for High Reliability and MEMs Applications","authors":"J. Naughton, M. Nelson","doi":"10.1109/ASMC.2006.1638729","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638729","url":null,"abstract":"It is widely known in the semiconductor industry that CMP induced micro-scratches can cause not only an initial failure but also a long-term reliability problem. Silicon oxide films doped with boron and phosphorus have been standard in pre-metal dielectric stacks but are prone to CMP micro scratching. A novel film stack was developed utilizing a thick undoped PECVD cap layer to mitigate device failure and reliability problems. The sequence of depositing the integral film layers in conjunction with the densification proved critical in maintaining device performance","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation and Design of an HDP-CVD Process for Planar Spacer Applications for Future DRAM Cell Concepts 面向未来DRAM单元概念的平面间隔应用的HDP-CVD工艺的仿真与设计
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638730
H. Weber, J. Radecker, G. Schulze-Icking-Konert, J. Bloking, W. Sabisch, A. Kersch, H. Whitesell, Y.S. Lee
{"title":"Simulation and Design of an HDP-CVD Process for Planar Spacer Applications for Future DRAM Cell Concepts","authors":"H. Weber, J. Radecker, G. Schulze-Icking-Konert, J. Bloking, W. Sabisch, A. Kersch, H. Whitesell, Y.S. Lee","doi":"10.1109/ASMC.2006.1638730","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638730","url":null,"abstract":"High density plasma chemical vapor deposition is a well known process for gap-fill applications. This paper describes the usage of high density plasma chemical vapor deposition to generate a buried isolation layer (planar spacer). A study to meet planar spacer requirements is presented based on simulations on reactor and feature scale. It explains variations from wafer center towards the edge in within-trench fill height uniformity, sidewall coverage and hat height. Plasma density variations across the wafer surface and subsequently deviations of incoming ions off the normal direction were found as the main contributor. Simulation results could be confirmed by several experiments. Based on these results a new type of high density plasma chemical vapor deposition process was designed to achieve homogenous within trench fill heights and pattern across the wafer and is therefore suitable for planar spacer applications","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129045400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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