Simulation and Design of an HDP-CVD Process for Planar Spacer Applications for Future DRAM Cell Concepts

Abstract

High density plasma chemical vapor deposition is a well known process for gap-fill applications. This paper describes the usage of high density plasma chemical vapor deposition to generate a buried isolation layer (planar spacer). A study to meet planar spacer requirements is presented based on simulations on reactor and feature scale. It explains variations from wafer center towards the edge in within-trench fill height uniformity, sidewall coverage and hat height. Plasma density variations across the wafer surface and subsequently deviations of incoming ions off the normal direction were found as the main contributor. Simulation results could be confirmed by several experiments. Based on these results a new type of high density plasma chemical vapor deposition process was designed to achieve homogenous within trench fill heights and pattern across the wafer and is therefore suitable for planar spacer applications