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Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics最新文献

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A new IGBT structure with a wider safe operating area (SOA) 具有更广泛安全操作区域的新IGBT结构(SOA)
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583697
N. Thaper, B. J. Baliga
{"title":"A new IGBT structure with a wider safe operating area (SOA)","authors":"N. Thaper, B. J. Baliga","doi":"10.1109/ISPSD.1994.583697","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583697","url":null,"abstract":"A new IGBT structure incorporating a shallow diverter between adjacent cells is proposed in this paper with the aim of widening the Forward Bias Safe Operating Area (FBSOA) of the IGBT. The latchup limit of the IGBT increased from 700 A/cm/sup 2/ to 1100 A/cm/sup 2/ in case of the n-channel IGBT and from 1200 A/cm/sup 2/ to 2100 A/cm/sup 2/ for the p-channel IGBT. Although there was a no improvement in the dynamic avalanche limit in the case of the p-channel IGBT, it improved significantly for the n-channel IGBT making its FBSOA much wider than that of the conventional IGBT. The incorporation of the diverter was found to result in an increase in the forward voltage drop (at a current density of 200 A/cm/sup 2/) from 1.7 V to 2.3 V and -2.3 V to -3.9 V for the n- and the p-channel IGBT, respectively.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122262775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Compact very high voltage CMOS compatible bipolar silicon-on-insulator transistor 紧凑的非常高电压CMOS兼容双极绝缘体上硅晶体管
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583667
A. Litwin, T. Arnborg
{"title":"Compact very high voltage CMOS compatible bipolar silicon-on-insulator transistor","authors":"A. Litwin, T. Arnborg","doi":"10.1109/ISPSD.1994.583667","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583667","url":null,"abstract":"A new type of bipolar transistor on SOI material (Silicon-On-Insulator) without buried layer has been fabricated in a standard 1.3 /spl mu/m CMOS process with only few additional mask steps. It is shown by measurements that the I-V characteristics of both pnp and npn transistors are comparable to conventional vertical transistors with buried layer. The voltage capability of devices made in thin silicon layers is substantially high and strongly affected by substrate bias effects. The transistors designed in a few micrometer thick silicon layer have a breakdown voltage BVceo of about 200 volts and also a remarkably high Early voltage, with highest measured value of 4000 V. The transistor will have a strong impact on the feasibility to realise mixed analogue and digital signal circuits with high and low voltage functions on the same chip.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134360775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1.5 GHz, 35-W Si-MOSFET with an internal matching circuit 带有内部匹配电路的1.5 GHz, 35w Si-MOSFET
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583817
E. Yanokura, T. Seki, I. Takei, Y. Maruyama, Y. Fujita, M. Katsueda, I. Yoshida, M. Ohnishi, K. Sekine
{"title":"A 1.5 GHz, 35-W Si-MOSFET with an internal matching circuit","authors":"E. Yanokura, T. Seki, I. Takei, Y. Maruyama, Y. Fujita, M. Katsueda, I. Yoshida, M. Ohnishi, K. Sekine","doi":"10.1109/ISPSD.1994.583817","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583817","url":null,"abstract":"We have developed a highly efficient Si power MOSFET that can operate at 1.5 GHz. This device has a double-ion-implanted layer in an offset region which achieves high drain current density as well as high breakdown voltage. It also has a 0.8-/spl mu/m Mo gate structure for high-frequency operation. In addition, we have successfully designed an internal matching circuit that overcomes the impedance-lowering problem of high-power MOSFETs operated at over 1 GHz. As a result, we obtain an output power of 35 W and a power-added efficiency of 50%, with excellent linearity of power gain.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132131554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A comparison of high frequency cell designs for high voltage DMOSFETs 高压dmosfet高频电池设计之比较
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583674
N. Thapar, B. J. Baliga
{"title":"A comparison of high frequency cell designs for high voltage DMOSFETs","authors":"N. Thapar, B. J. Baliga","doi":"10.1109/ISPSD.1994.583674","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583674","url":null,"abstract":"To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R/sub on,sp/) and the specific input capacitance (C/sub in,sp/). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R/sub on/C/sub in/ product. The terrace gate design on ALL, with 6000 /spl Aring/ field oxide under the terrace gate region resulted in a R/sub on/C/sub in/ product of 603 /spl Omega/-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P/sup +/ diffusion, the gate-drain component (C/sub gd/) of the input capacitance (C/sub in/) was reduced by moving the floating P/sup +/ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R/sub on/C/sub in/ product as a function of the position of the floating P/sup +/ edge, lowest R/sub on/C/sub in/ products of 452 /spl Omega/-pf and 360 /spl Omega/-pf were obtained for the ALL and CL, respectively. Although the R/sub on/C/sub in/ product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/ for the ALL and 137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/ for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130188634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Cosmic ray induced breakdown in high voltage semiconductor devices, microscopic model and phenomenological lifetime prediction 高压半导体器件中的宇宙射线致击穿，微观模型和现象学寿命预测
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583762
H. Zeller
{"title":"Cosmic ray induced breakdown in high voltage semiconductor devices, microscopic model and phenomenological lifetime prediction","authors":"H. Zeller","doi":"10.1109/ISPSD.1994.583762","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583762","url":null,"abstract":"Recently a new cosmic ray induced failure mode of high current-high voltage semiconductor devices has been discovered. The failure affects diodes, thyristors and GTO's as well. it consists of a localised breakdown in the bulk of the device and is not related to junction termination instabilities. The onset of the breakdown occurs without a precursor within a few nanoseconds. The failure rate is constant in time, strongly dependent on applied voltage and nearly independent of temperature. The effect is reduced by screening and thus it is generally believed that the failure is cosmic ray induced. We have measured GTO's, diodes and thyristors of 2.5 kV and 4.5 kV ratings at various test voltages and also have obtained field data from customers.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132876964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Thermal behaviour of lateral power devices on SOI substrates SOI基板上横向功率器件的热性能
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583671
H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose
{"title":"Thermal behaviour of lateral power devices on SOI substrates","authors":"H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose","doi":"10.1109/ISPSD.1994.583671","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583671","url":null,"abstract":"Simulated temperature distributions for SOI-structures with various film thicknesses for different operating conditions (on state, turn-off and pulse overload) and different SOI sheet thicknesses (20 /spl mu/m, 5 /spl mu/m) are presented and discussed. The temperature increase was in the range between 5 K and 400 K. The calculated results have been verified experimentally for a fabricated device. An important result is the reduced pulse overload capacity of thin SOI-devices in the 10 /spl mu/s to 100 /spl mu/s range. Consequences for application of SOI-devices are discussed.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126150850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A comparative study of physical and subcircuit models for MOS-gated power devices mos门控功率器件物理模型与子电路模型的比较研究
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583752
N. Andersson, M. Gronlund, P. Kuivalainen, H. Pohjonen
{"title":"A comparative study of physical and subcircuit models for MOS-gated power devices","authors":"N. Andersson, M. Gronlund, P. Kuivalainen, H. Pohjonen","doi":"10.1109/ISPSD.1994.583752","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583752","url":null,"abstract":"We have developed a new extensive model library for MOS-gated power devices aimed for CAD and the simulation of power integrated circuits and power electronics. Comparisons between the compact physical models implemented in an open circuit simulator, Aplac, and semiempirical SPICE compatible subcircuit models show that the accuracy of the subcircuit models approaches that of the physical models, if the components of the subcircuit are modelled properly.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A reverse-channel, high-voltage lateral IGBT 一个反向通道，高压横向IGBT
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583647
T. Chow, D. Pattanayak, B. J. Baliga, M. Adler
{"title":"A reverse-channel, high-voltage lateral IGBT","authors":"T. Chow, D. Pattanayak, B. J. Baliga, M. Adler","doi":"10.1109/ISPSD.1994.583647","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583647","url":null,"abstract":"A novel reverse-channel lateral IGBT has been studied with numerical simulations and demonstrated experimentally for the first time. It exhibits a negative differential resistance (NDR) region, which is dependent on the gate voltage and has large peak to valley ratios (10 to >1000), in the I-V characteristics. Also, during dynamic switching, it has been shown to be self-current limiting and hence not to latch up.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Reduction of thermomechanical stress by applying a low temperature joining technique 通过应用低温连接技术降低热机械应力
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583736
S. Klaka, R. Sittig
{"title":"Reduction of thermomechanical stress by applying a low temperature joining technique","authors":"S. Klaka, R. Sittig","doi":"10.1109/ISPSD.1994.583736","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583736","url":null,"abstract":"Schwarzbauer and Kuhnert proposed a novel low temperature joining (LTJ) technique to connect silicon wafers with molybdenum backplates [1989, 1991]. Investigation of the bond build-up led to the idea to influence the thermomechanical stresses between bonded materials. By measuring the temperature dependent bow of silicon disks of 26 mm diameter joined to molybdenum backplates the stresses inside both materials were determined. The experiments revealed that variation of process parameters allows one to control the temperature at which no stress occurs between the joined disks. This can be used to considerably reduce thermomechanical stress caused by temperature cycling.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123874104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A novel high voltage bipolar technology featuring trench-isolated base 一种新型的沟槽隔离基极高压双极技术
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583748
H. Kim, J. Jin, C. Jeoun, Y. Choi, B. Kwon, S. Lim, K. Choi
{"title":"A novel high voltage bipolar technology featuring trench-isolated base","authors":"H. Kim, J. Jin, C. Jeoun, Y. Choi, B. Kwon, S. Lim, K. Choi","doi":"10.1109/ISPSD.1994.583748","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583748","url":null,"abstract":"In this paper, we present a novel bipolar technology featuring the trench-isolated base. When employed for a conventional 2 /spl mu/m process, the trench isolation reduces both the surface leakage and current gain of the parasitic lateral pnp transistor by at least one order, which results in the improvement of the punchthrough-induced breakdown behavior by almost a factor of two. The depletion capacitance is also diminished by about 60% thanks to the decrease of the effective base-collector junction area, suggesting that the trench isolation is a viable approach even for high frequency as well as for high voltage applications.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116780330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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